From 20cf599d89115f6f7bc0e13a2629fffab9dcf0d2 Mon Sep 17 00:00:00 2001 From: Daniel Cujba Date: Tue, 13 Apr 2021 00:07:23 +0300 Subject: [PATCH] Initial Commit with everything done --- Project 1/And.hdl | 19 ++++++++++++ Project 1/And16.hdl | 32 ++++++++++++++++++++ Project 1/DMux.hdl | 20 ++++++++++++ Project 1/DMux4Way.hdl | 31 +++++++++++++++++++ Project 1/DMux8Way.hdl | 46 ++++++++++++++++++++++++++++ Project 1/Mux.hdl | 25 +++++++++++++++ Project 1/Mux16.hdl | 33 ++++++++++++++++++++ Project 1/Mux4Way16.hdl | 22 ++++++++++++++ Project 1/Mux8Way16.hdl | 28 +++++++++++++++++ Project 1/Not.hdl | 17 +++++++++++ Project 1/Not16.hdl | 32 ++++++++++++++++++++ Project 1/Or.hdl | 22 ++++++++++++++ Project 1/Or16.hdl | 32 ++++++++++++++++++++ Project 1/Or8Way.hdl | 23 ++++++++++++++ Project 1/Xor.hdl | 21 +++++++++++++ Project 2/ALU.hdl | 63 ++++++++++++++++++++++++++++++++++++++ Project 2/Add16.hdl | 33 ++++++++++++++++++++ Project 2/FullAdder.hdl | 19 ++++++++++++ Project 2/HalfAdder.hdl | 18 +++++++++++ Project 2/Inc16.hdl | 33 ++++++++++++++++++++ Project 3/Bit.hdl | 25 +++++++++++++++ Project 3/PC.hdl | 32 ++++++++++++++++++++ Project 3/RAM16K.hdl | 25 +++++++++++++++ Project 3/RAM4K.hdl | 29 ++++++++++++++++++ Project 3/RAM512.hdl | 29 ++++++++++++++++++ Project 3/RAM64.hdl | 31 +++++++++++++++++++ Project 3/RAM8.hdl | 29 ++++++++++++++++++ Project 3/Register.hdl | 34 +++++++++++++++++++++ Project 4/Fill.asm | 59 ++++++++++++++++++++++++++++++++++++ Project 4/Mult.asm | 26 ++++++++++++++++ Project 5/CPU.hdl | 67 +++++++++++++++++++++++++++++++++++++++++ Project 5/Computer.hdl | 26 ++++++++++++++++ Project 5/Memory.hdl | 38 +++++++++++++++++++++++ 33 files changed, 1019 insertions(+) create mode 100644 Project 1/And.hdl create mode 100644 Project 1/And16.hdl create mode 100644 Project 1/DMux.hdl create mode 100644 Project 1/DMux4Way.hdl create mode 100644 Project 1/DMux8Way.hdl create mode 100644 Project 1/Mux.hdl create mode 100644 Project 1/Mux16.hdl create mode 100644 Project 1/Mux4Way16.hdl create mode 100644 Project 1/Mux8Way16.hdl create mode 100644 Project 1/Not.hdl create mode 100644 Project 1/Not16.hdl create mode 100644 Project 1/Or.hdl create mode 100644 Project 1/Or16.hdl create mode 100644 Project 1/Or8Way.hdl create mode 100644 Project 1/Xor.hdl create mode 100644 Project 2/ALU.hdl create mode 100644 Project 2/Add16.hdl create mode 100644 Project 2/FullAdder.hdl create mode 100644 Project 2/HalfAdder.hdl create mode 100644 Project 2/Inc16.hdl create mode 100644 Project 3/Bit.hdl create mode 100644 Project 3/PC.hdl create mode 100644 Project 3/RAM16K.hdl create mode 100644 Project 3/RAM4K.hdl create mode 100644 Project 3/RAM512.hdl create mode 100644 Project 3/RAM64.hdl create mode 100644 Project 3/RAM8.hdl create mode 100644 Project 3/Register.hdl create mode 100644 Project 4/Fill.asm create mode 100644 Project 4/Mult.asm create mode 100644 Project 5/CPU.hdl create mode 100644 Project 5/Computer.hdl create mode 100644 Project 5/Memory.hdl diff --git a/Project 1/And.hdl b/Project 1/And.hdl new file mode 100644 index 0000000..ed62fd1 --- /dev/null +++ b/Project 1/And.hdl @@ -0,0 +1,19 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/And.hdl + +/** + * And gate: + * out = 1 if (a == 1 and b == 1) + * 0 otherwise + */ + +CHIP And { + IN a, b; + OUT out; + + PARTS: + Nand(a=a,b=b,out=out1); + Not(in=out1,out=out); +} diff --git a/Project 1/And16.hdl b/Project 1/And16.hdl new file mode 100644 index 0000000..063d9c1 --- /dev/null +++ b/Project 1/And16.hdl @@ -0,0 +1,32 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/And16.hdl + +/** + * 16-bit bitwise And: + * for i = 0..15: out[i] = (a[i] and b[i]) + */ + +CHIP And16 { + IN a[16], b[16]; + OUT out[16]; + + PARTS: + And(a=a[0],b=b[0],out=out[0]); + And(a=a[1],b=b[1],out=out[1]); + And(a=a[2],b=b[2],out=out[2]); + And(a=a[3],b=b[3],out=out[3]); + And(a=a[4],b=b[4],out=out[4]); + And(a=a[5],b=b[5],out=out[5]); + And(a=a[6],b=b[6],out=out[6]); + And(a=a[7],b=b[7],out=out[7]); + And(a=a[8],b=b[8],out=out[8]); + And(a=a[9],b=b[9],out=out[9]); + And(a=a[10],b=b[10],out=out[10]); + And(a=a[11],b=b[11],out=out[11]); + And(a=a[12],b=b[12],out=out[12]); + And(a=a[13],b=b[13],out=out[13]); + And(a=a[14],b=b[14],out=out[14]); + And(a=a[15],b=b[15],out=out[15]); +} \ No newline at end of file diff --git a/Project 1/DMux.hdl b/Project 1/DMux.hdl new file mode 100644 index 0000000..68dd007 --- /dev/null +++ b/Project 1/DMux.hdl @@ -0,0 +1,20 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/DMux.hdl + +/** + * Demultiplexor: + * {a, b} = {in, 0} if sel == 0 + * {0, in} if sel == 1 + */ + +CHIP DMux { + IN in, sel; + OUT a, b; + + PARTS: + And(a=in,b=sel,out=b); + Not(in=sel,out=negSel); + And(a=in,b=negSel,out=a); +} diff --git a/Project 1/DMux4Way.hdl b/Project 1/DMux4Way.hdl new file mode 100644 index 0000000..573afd2 --- /dev/null +++ b/Project 1/DMux4Way.hdl @@ -0,0 +1,31 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/DMux4Way.hdl + +/** + * 4-way demultiplexor: + * {a, b, c, d} = {in, 0, 0, 0} if sel == 00 + * {0, in, 0, 0} if sel == 01 + * {0, 0, in, 0} if sel == 10 + * {0, 0, 0, in} if sel == 11 + */ + +CHIP DMux4Way { + IN in, sel[2]; + OUT a, b, c, d; + + PARTS: + Not(in=sel[0],out=negSel1); + Not(in=sel[1],out=negSel2); + + And(a=in,b=sel[0],out=out1); + And(a=in,b=negSel1,out=out2); + And(a=in,b=sel[1],out=out3); + And(a=in,b=negSel2,out=out4); + + And(a=out1,b=out3,out=d); + And(a=out2,b=out3,out=c); + And(a=out1,b=out4,out=b); + And(a=out2,b=out4,out=a); +} \ No newline at end of file diff --git a/Project 1/DMux8Way.hdl b/Project 1/DMux8Way.hdl new file mode 100644 index 0000000..7d65bc2 --- /dev/null +++ b/Project 1/DMux8Way.hdl @@ -0,0 +1,46 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/DMux8Way.hdl + +/** + * 8-way demultiplexor: + * {a, b, c, d, e, f, g, h} = {in, 0, 0, 0, 0, 0, 0, 0} if sel == 000 + * {0, in, 0, 0, 0, 0, 0, 0} if sel == 001 + * etc. + * {0, 0, 0, 0, 0, 0, 0, in} if sel == 111 + */ + +CHIP DMux8Way { + IN in, sel[3]; + OUT a, b, c, d, e, f, g, h; + + PARTS: + Not(in=sel[0],out=negSel1); + Not(in=sel[1],out=negSel2); + Not(in=sel[2],out=negSel3); + + And(a=in,b=sel[0],out=out1); + And(a=in,b=negSel1,out=out2); + And(a=in,b=sel[1],out=out3); + And(a=in,b=negSel2,out=out4); + And(a=in,b=sel[2],out=out5); + And(a=in,b=negSel3,out=out6); + + And(a=out1,b=out3,out=outX11); + And(a=out2,b=out3,out=outX10); + And(a=out1,b=out4,out=outX01); + And(a=out2,b=out4,out=outX00); + + And(a=outX11,b=out5,out=h); + And(a=outX10,b=out5,out=g); + And(a=outX01,b=out5,out=f); + And(a=outX00,b=out5,out=e); + And(a=outX11,b=out6,out=d); + And(a=outX10,b=out6,out=c); + And(a=outX01,b=out6,out=b); + And(a=outX00,b=out6,out=a); + + + +} \ No newline at end of file diff --git a/Project 1/Mux.hdl b/Project 1/Mux.hdl new file mode 100644 index 0000000..c992363 --- /dev/null +++ b/Project 1/Mux.hdl @@ -0,0 +1,25 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/Mux.hdl + +/** + * Multiplexor: + * out = a if sel == 0 + * b otherwise + */ + +CHIP Mux { + IN a, b, sel; + OUT out; + + PARTS: + Not(in=a,out=negA); + Not(in=b,out=negB); + Not(in=sel,out=negSel); + And(a=a,b=b,out=out1); + And(a=a,b=negSel,out=out2); + And(a=b,b=sel,out=out3); + Or(a=out1,b=out2,out=xOut); + Or(a=xOut,b=out3,out=out); +} \ No newline at end of file diff --git a/Project 1/Mux16.hdl b/Project 1/Mux16.hdl new file mode 100644 index 0000000..8090ca6 --- /dev/null +++ b/Project 1/Mux16.hdl @@ -0,0 +1,33 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/Mux16.hdl + +/** + * 16-bit multiplexor: + * for i = 0..15 out[i] = a[i] if sel == 0 + * b[i] if sel == 1 + */ + +CHIP Mux16 { + IN a[16], b[16], sel; + OUT out[16]; + + PARTS: + Mux(a=a[0],b=b[0],sel=sel,out=out[0]); + Mux(a=a[1],b=b[1],sel=sel,out=out[1]); + Mux(a=a[2],b=b[2],sel=sel,out=out[2]); + Mux(a=a[3],b=b[3],sel=sel,out=out[3]); + Mux(a=a[4],b=b[4],sel=sel,out=out[4]); + Mux(a=a[5],b=b[5],sel=sel,out=out[5]); + Mux(a=a[6],b=b[6],sel=sel,out=out[6]); + Mux(a=a[7],b=b[7],sel=sel,out=out[7]); + Mux(a=a[8],b=b[8],sel=sel,out=out[8]); + Mux(a=a[9],b=b[9],sel=sel,out=out[9]); + Mux(a=a[10],b=b[10],sel=sel,out=out[10]); + Mux(a=a[11],b=b[11],sel=sel,out=out[11]); + Mux(a=a[12],b=b[12],sel=sel,out=out[12]); + Mux(a=a[13],b=b[13],sel=sel,out=out[13]); + Mux(a=a[14],b=b[14],sel=sel,out=out[14]); + Mux(a=a[15],b=b[15],sel=sel,out=out[15]); +} \ No newline at end of file diff --git a/Project 1/Mux4Way16.hdl b/Project 1/Mux4Way16.hdl new file mode 100644 index 0000000..4aa3fc5 --- /dev/null +++ b/Project 1/Mux4Way16.hdl @@ -0,0 +1,22 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/Mux4Way16.hdl + +/** + * 4-way 16-bit multiplexor: + * out = a if sel == 00 + * b if sel == 01 + * c if sel == 10 + * d if sel == 11 + */ + +CHIP Mux4Way16 { + IN a[16], b[16], c[16], d[16], sel[2]; + OUT out[16]; + + PARTS: + Mux16(a=a,b=b,sel=sel[0],out=out1); + Mux16(a=c,b=d,sel=sel[0],out=out2); + Mux16(a=out1,b=out2,sel=sel[1],out=out); +} \ No newline at end of file diff --git a/Project 1/Mux8Way16.hdl b/Project 1/Mux8Way16.hdl new file mode 100644 index 0000000..0f1b6f2 --- /dev/null +++ b/Project 1/Mux8Way16.hdl @@ -0,0 +1,28 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/Mux8Way16.hdl + +/** + * 8-way 16-bit multiplexor: + * out = a if sel == 000 + * b if sel == 001 + * etc. + * h if sel == 111 + */ + +CHIP Mux8Way16 { + IN a[16], b[16], c[16], d[16], + e[16], f[16], g[16], h[16], + sel[3]; + OUT out[16]; + + PARTS: + Mux16(a=a,b=b,sel=sel[0],out=out11); + Mux16(a=c,b=d,sel=sel[0],out=out12); + Mux16(a=e,b=f,sel=sel[0],out=out13); + Mux16(a=g,b=h,sel=sel[0],out=out14); + Mux16(a=out11,b=out12,sel=sel[1],out=out21); + Mux16(a=out13,b=out14,sel=sel[1],out=out22); + Mux16(a=out21,b=out22,sel=sel[2],out=out); +} \ No newline at end of file diff --git a/Project 1/Not.hdl b/Project 1/Not.hdl new file mode 100644 index 0000000..f746927 --- /dev/null +++ b/Project 1/Not.hdl @@ -0,0 +1,17 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/Not.hdl + +/** + * Not gate: + * out = not in + */ + +CHIP Not { + IN in; + OUT out; + + PARTS: + Nand(a=in,b=in,out=out); +} \ No newline at end of file diff --git a/Project 1/Not16.hdl b/Project 1/Not16.hdl new file mode 100644 index 0000000..a1386c8 --- /dev/null +++ b/Project 1/Not16.hdl @@ -0,0 +1,32 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/Not16.hdl + +/** + * 16-bit Not: + * for i=0..15: out[i] = not in[i] + */ + +CHIP Not16 { + IN in[16]; + OUT out[16]; + + PARTS: + Not(in=in[0],out=out[0]); + Not(in=in[1],out=out[1]); + Not(in=in[2],out=out[2]); + Not(in=in[3],out=out[3]); + Not(in=in[4],out=out[4]); + Not(in=in[5],out=out[5]); + Not(in=in[6],out=out[6]); + Not(in=in[7],out=out[7]); + Not(in=in[8],out=out[8]); + Not(in=in[9],out=out[9]); + Not(in=in[10],out=out[10]); + Not(in=in[11],out=out[11]); + Not(in=in[12],out=out[12]); + Not(in=in[13],out=out[13]); + Not(in=in[14],out=out[14]); + Not(in=in[15],out=out[15]); +} \ No newline at end of file diff --git a/Project 1/Or.hdl b/Project 1/Or.hdl new file mode 100644 index 0000000..c08abd0 --- /dev/null +++ b/Project 1/Or.hdl @@ -0,0 +1,22 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/Or.hdl + + /** + * Or gate: + * out = 1 if (a == 1 or b == 1) + * 0 otherwise + */ + +CHIP Or { + IN a, b; + OUT out; + + PARTS: + Not(in=b,out=negB); + Not(in=a,out=negA); + Nand(a=a,b=negB,out=out1); + Nand(a=out1,b=b,out=out2); + Nand(a=negA,b=out2,out=out); +} diff --git a/Project 1/Or16.hdl b/Project 1/Or16.hdl new file mode 100644 index 0000000..a0b1f0e --- /dev/null +++ b/Project 1/Or16.hdl @@ -0,0 +1,32 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/Or16.hdl + +/** + * 16-bit bitwise Or: + * for i = 0..15 out[i] = (a[i] or b[i]) + */ + +CHIP Or16 { + IN a[16], b[16]; + OUT out[16]; + + PARTS: + Or(a=a[0],b=b[0],out=out[0]); + Or(a=a[1],b=b[1],out=out[1]); + Or(a=a[2],b=b[2],out=out[2]); + Or(a=a[3],b=b[3],out=out[3]); + Or(a=a[4],b=b[4],out=out[4]); + Or(a=a[5],b=b[5],out=out[5]); + Or(a=a[6],b=b[6],out=out[6]); + Or(a=a[7],b=b[7],out=out[7]); + Or(a=a[8],b=b[8],out=out[8]); + Or(a=a[9],b=b[9],out=out[9]); + Or(a=a[10],b=b[10],out=out[10]); + Or(a=a[11],b=b[11],out=out[11]); + Or(a=a[12],b=b[12],out=out[12]); + Or(a=a[13],b=b[13],out=out[13]); + Or(a=a[14],b=b[14],out=out[14]); + Or(a=a[15],b=b[15],out=out[15]); +} \ No newline at end of file diff --git a/Project 1/Or8Way.hdl b/Project 1/Or8Way.hdl new file mode 100644 index 0000000..f6b757d --- /dev/null +++ b/Project 1/Or8Way.hdl @@ -0,0 +1,23 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/Or8Way.hdl + +/** + * 8-way Or: + * out = (in[0] or in[1] or ... or in[7]) + */ + +CHIP Or8Way { + IN in[8]; + OUT out; + + PARTS: + Or(a=in[0],b=in[1],out=out1); + Or(a=in[2],b=in[3],out=out2); + Or(a=in[4],b=in[5],out=out3); + Or(a=in[6],b=in[7],out=out4); + Or(a=out1,b=out2,out=out11); + Or(a=out3,b=out4,out=out12); + Or(a=out11,b=out12,out=out); +} \ No newline at end of file diff --git a/Project 1/Xor.hdl b/Project 1/Xor.hdl new file mode 100644 index 0000000..2eaa9bb --- /dev/null +++ b/Project 1/Xor.hdl @@ -0,0 +1,21 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/01/Xor.hdl + +/** + * Exclusive-or gate: + * out = not (a == b) + */ + +CHIP Xor { + IN a, b; + OUT out; + + PARTS: + Not(in=a,out=negA); + Not(in=b,out=negB); + Nand(a=a,b=negB,out=out1); + Nand(a=b,b=negA,out=out2); + Nand(a=out1,b=out2,out=out); +} \ No newline at end of file diff --git a/Project 2/ALU.hdl b/Project 2/ALU.hdl new file mode 100644 index 0000000..9dc4a3b --- /dev/null +++ b/Project 2/ALU.hdl @@ -0,0 +1,63 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/02/ALU.hdl + +/** + * The ALU (Arithmetic Logic Unit). + * Computes one of the following functions: + * x+y, x-y, y-x, 0, 1, -1, x, y, -x, -y, !x, !y, + * x+1, y+1, x-1, y-1, x&y, x|y on two 16-bit inputs, + * according to 6 input bits denoted notZX,nx,notZY,ny,f,no. + * In addition, the ALU computes two 1-bit outputs: + * if the ALU output == 0, zr is set to 1; otherwise zr is set to 0; + * if the ALU output < 0, ng is set to 1; otherwise ng is set to 0. + */ + +// Implementation: the ALU logic manipulates the x and y inputs +// and operates on the resulting values, as follows: +// if (notZX == 1) set x = 0 // 16-bit constant +// if (nx == 1) set x = !x // bitwise not +// if (notZY == 1) set y = 0 // 16-bit constant +// if (ny == 1) set y = !y // bitwise not +// if (f == 1) set out = x + y // integer 2's complement addition +// if (f == 0) set out = x & y // bitwise and +// if (no == 1) set out = !out // bitwise not +// if (out == 0) set zr = 1 +// if (out < 0) set ng = 1 + +CHIP ALU { + IN + x[16], y[16], // 16-bit inputs + zx, // zero the x input? + nx, // negate the x input? + zy, // zero the y input? + ny, // negate the y input? + f, // compute out = x + y (if 1) or x & y (if 0) + no; // negate the out output? + + OUT + out[16], // 16-bit output + zr, // 1 if (out == 0), 0 otherwise + ng; // 1 if (out < 0), 0 otherwise + + PARTS: + // Put you code here: + Not(in=zx,out=notZX); + Not(in=zy,out=notZY); + And16(a[0]=notZX,a[1]=notZX,a[2]=notZX,a[3]=notZX,a[4]=notZX,a[5]=notZX,a[6]=notZX,a[7]=notZX,a[8]=notZX,a[9]=notZX,a[10]=notZX,a[11]=notZX,a[12]=notZX,a[13]=notZX,a[14]=notZX,a[15]=notZX,b=x,out=ZX); + And16(a[0]=notZY,a[1]=notZY,a[2]=notZY,a[3]=notZY,a[4]=notZY,a[5]=notZY,a[6]=notZY,a[7]=notZY,a[8]=notZY,a[9]=notZY,a[10]=notZY,a[11]=notZY,a[12]=notZY,a[13]=notZY,a[14]=notZY,a[15]=notZY,b=y,out=ZY); + Xor16(a[0]=nx,a[1]=nx,a[2]=nx,a[3]=nx,a[4]=nx,a[5]=nx,a[6]=nx,a[7]=nx,a[8]=nx,a[9]=nx,a[10]=nx,a[11]=nx,a[12]=nx,a[13]=nx,a[14]=nx,a[15]=nx,b=ZX,out=NX); + Xor16(a[0]=ny,a[1]=ny,a[2]=ny,a[3]=ny,a[4]=ny,a[5]=ny,a[6]=ny,a[7]=ny,a[8]=ny,a[9]=ny,a[10]=ny,a[11]=ny,a[12]=ny,a[13]=ny,a[14]=ny,a[15]=ny,b=ZY,out=NY); + Add16(a=NX,b=NY,out=sumout); + And16(a=NX,b=NY,out=andout); + Not(in=f,out=notF); + And16(a[0]=f,a[1]=f,a[2]=f,a[3]=f,a[4]=f,a[5]=f,a[6]=f,a[7]=f,a[8]=f,a[9]=f,a[10]=f,a[11]=f,a[12]=f,a[13]=f,a[14]=f,a[15]=f,b=sumout,out=out1); + And16(a[0]=notF,a[1]=notF,a[2]=notF,a[3]=notF,a[4]=notF,a[5]=notF,a[6]=notF,a[7]=notF,a[8]=notF,a[9]=notF,a[10]=notF,a[11]=notF,a[12]=notF,a[13]=notF,a[14]=notF,a[15]=notF,b=andout,out=out2); + Xor16(a=out1,b=out2,out=out3); + Xor16(a[0]=no,a[1]=no,a[2]=no,a[3]=no,a[4]=no,a[5]=no,a[6]=no,a[7]=no,a[8]=no,a[9]=no,a[10]=no,a[11]=no,a[12]=no,a[13]=no,a[14]=no,a[15]=no,b=out3,out=output); + And16(a=output,b=output,out=out); + Not16(in=output,out=notOut); + Add16Way(in=notOut,out=zr); + CheckPin16(in=output,out=ng); +} \ No newline at end of file diff --git a/Project 2/Add16.hdl b/Project 2/Add16.hdl new file mode 100644 index 0000000..49e86f1 --- /dev/null +++ b/Project 2/Add16.hdl @@ -0,0 +1,33 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/02/Adder16.hdl + +/** + * Adds two 16-bit values. + * The most significant carry bit is ignored. + */ + +CHIP Add16 { + IN a[16], b[16]; + OUT out[16]; + + PARTS: + // Put you code here: + FullAdder(a=a[0],b=b[0],c=false,sum=out[0],carry=carry1); + FullAdder(a=a[1],b=b[1],c=carry1,sum=out[1],carry=carry2); + FullAdder(a=a[2],b=b[2],c=carry2,sum=out[2],carry=carry3); + FullAdder(a=a[3],b=b[3],c=carry3,sum=out[3],carry=carry4); + FullAdder(a=a[4],b=b[4],c=carry4,sum=out[4],carry=carry5); + FullAdder(a=a[5],b=b[5],c=carry5,sum=out[5],carry=carry6); + FullAdder(a=a[6],b=b[6],c=carry6,sum=out[6],carry=carry7); + FullAdder(a=a[7],b=b[7],c=carry7,sum=out[7],carry=carry8); + FullAdder(a=a[8],b=b[8],c=carry8,sum=out[8],carry=carry9); + FullAdder(a=a[9],b=b[9],c=carry9,sum=out[9],carry=carry10); + FullAdder(a=a[10],b=b[10],c=carry10,sum=out[10],carry=carry11); + FullAdder(a=a[11],b=b[11],c=carry11,sum=out[11],carry=carry12); + FullAdder(a=a[12],b=b[12],c=carry12,sum=out[12],carry=carry13); + FullAdder(a=a[13],b=b[13],c=carry13,sum=out[13],carry=carry14); + FullAdder(a=a[14],b=b[14],c=carry14,sum=out[14],carry=carry15); + FullAdder(a=a[15],b=b[15],c=carry15,sum=out[15],carry=carry16); +} \ No newline at end of file diff --git a/Project 2/FullAdder.hdl b/Project 2/FullAdder.hdl new file mode 100644 index 0000000..bbbc434 --- /dev/null +++ b/Project 2/FullAdder.hdl @@ -0,0 +1,19 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/02/FullAdder.hdl + +/** + * Computes the sum of three bits. + */ + +CHIP FullAdder { + IN a, b, c; // 1-bit inputs + OUT sum, // Right bit of a + b + c + carry; // Left bit of a + b + c + + PARTS: + HalfAdder(a=a,b=b,sum=sum1,carry=carry1); + HalfAdder(a=sum1,b=c,sum=sum,carry=carry2); + Xor(a=carry1,b=carry2,out=carry); +} \ No newline at end of file diff --git a/Project 2/HalfAdder.hdl b/Project 2/HalfAdder.hdl new file mode 100644 index 0000000..7818e99 --- /dev/null +++ b/Project 2/HalfAdder.hdl @@ -0,0 +1,18 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/02/HalfAdder.hdl + +/** + * Computes the sum of two bits. + */ + +CHIP HalfAdder { + IN a, b; // 1-bit inputs + OUT sum, // Right bit of a + b + carry; // Left bit of a + b + + PARTS: + Xor(a=a,b=b,out=sum); + And(a=a,b=b,out=carry); +} diff --git a/Project 2/Inc16.hdl b/Project 2/Inc16.hdl new file mode 100644 index 0000000..bb66d9b --- /dev/null +++ b/Project 2/Inc16.hdl @@ -0,0 +1,33 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/02/Inc16.hdl + +/** + * 16-bit incrementer: + * out = in + 1 (arithmetic addition) + */ + +CHIP Inc16 { + IN in[16]; + OUT out[16]; + + PARTS: + HalfAdder(a=in[0],b=true,sum=out[0],carry=carry1); + HalfAdder(a=in[1],b=carry1,sum=out[1],carry=carry2); + HalfAdder(a=in[2],b=carry2,sum=out[2],carry=carry3); + HalfAdder(a=in[3],b=carry3,sum=out[3],carry=carry4); + HalfAdder(a=in[4],b=carry4,sum=out[4],carry=carry5); + HalfAdder(a=in[5],b=carry5,sum=out[5],carry=carry6); + HalfAdder(a=in[6],b=carry6,sum=out[6],carry=carry7); + HalfAdder(a=in[7],b=carry7,sum=out[7],carry=carry8); + HalfAdder(a=in[8],b=carry8,sum=out[8],carry=carry9); + HalfAdder(a=in[9],b=carry9,sum=out[9],carry=carry10); + HalfAdder(a=in[10],b=carry10,sum=out[10],carry=carry11); + HalfAdder(a=in[11],b=carry11,sum=out[11],carry=carry12); + HalfAdder(a=in[12],b=carry12,sum=out[12],carry=carry13); + HalfAdder(a=in[13],b=carry13,sum=out[13],carry=carry14); + HalfAdder(a=in[14],b=carry14,sum=out[14],carry=carry15); + HalfAdder(a=in[15],b=carry15,sum=out[15],carry=carry16); + +} \ No newline at end of file diff --git a/Project 3/Bit.hdl b/Project 3/Bit.hdl new file mode 100644 index 0000000..4172624 --- /dev/null +++ b/Project 3/Bit.hdl @@ -0,0 +1,25 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/03/a/Bit.hdl + +/** + * 1-bit register: + * If load[t] == 1 then out[t+1] = in[t] + * else out does not change (out[t+1] = out[t]) + */ + +CHIP Bit { + IN in, load; + OUT out; + + PARTS: + // Put your code here: + Not(in=load,out=negLoad); + And(a=in,b=load,out=out1); + And(a=b,b=negLoad,out=out2); + Xor(a=out1,b=out2,out=a); + DFF(in=a,out=b,out=out); + + +} \ No newline at end of file diff --git a/Project 3/PC.hdl b/Project 3/PC.hdl new file mode 100644 index 0000000..eac9302 --- /dev/null +++ b/Project 3/PC.hdl @@ -0,0 +1,32 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/03/a/PC.hdl + +/** + * A 16-bit counter with load and reset control bits. + * if (reset[t] == 1) out[t+1] = 0 + * else if (load[t] == 1) out[t+1] = in[t] + * else if (inc[t] == 1) out[t+1] = out[t] + 1 (integer addition) + * else out[t+1] = out[t] + */ + +CHIP PC { + IN in[16],load,inc,reset; + OUT out[16]; + + PARTS: + + // Put your code here: + Or(a=reset,b=load,out=load1); + Or(a=load1,b=inc,out=trueLoad); + Inc16(in=b,out=incIn); + And16(a=incIn,b[0]=inc,b[1]=inc,b[2]=inc,b[3]=inc,b[4]=inc,b[5]=inc,b[6]=inc,b[7]=inc,b[8]=inc,b[9]=inc,b[10]=inc,b[11]=inc,b[12]=inc,b[13]=inc,b[14]=inc,b[15]=inc,out=in1); + Not(in=reset,out=negReset); + And16(a=in,b[0]=negReset,b[1]=negReset,b[2]=negReset,b[3]=negReset,b[4]=negReset,b[5]=negReset,b[6]=negReset,b[7]=negReset,b[8]=negReset,b[9]=negReset,b[10]=negReset,b[11]=negReset,b[12]=negReset,b[13]=negReset,b[14]=negReset,b[15]=negReset,out=in2); + Not(in=load,out=negLoad); + And(a=negReset,b=negLoad,out=out1); + And(a=inc,b=out1,out=sel); + Mux16(a=in2,b=in1,sel=sel,out=trueIn); + Register(in=trueIn,load=trueLoad,out=out,out=b); +} \ No newline at end of file diff --git a/Project 3/RAM16K.hdl b/Project 3/RAM16K.hdl new file mode 100644 index 0000000..970a30c --- /dev/null +++ b/Project 3/RAM16K.hdl @@ -0,0 +1,25 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/03/b/RAM16K.hdl + +/** + * Memory of 16K registers, each 16 bit-wide. Out holds the value + * stored at the memory location specified by address. If load==1, then + * the in value is loaded into the memory location specified by address + * (the loaded value will be emitted to out from the next time step onward). + */ + +CHIP RAM16K { + IN in[16], load, address[14]; + OUT out[16]; + + PARTS: + // Put your code here: + DMux4Way(in=load,sel[0]=address[0],sel[1]=address[1],a=a,b=b,c=c,d=d); + RAM4K(in=in,load=a,address[0]=address[2],address[1]=address[3],address[2]=address[4],address[3]=address[5],address[4]=address[6],address[5]=address[7],address[6]=address[8],address[7]=address[9],address[8]=address[10],address[9]=address[11],address[10]=address[12],address[11]=address[13],out=out1); + RAM4K(in=in,load=b,address[0]=address[2],address[1]=address[3],address[2]=address[4],address[3]=address[5],address[4]=address[6],address[5]=address[7],address[6]=address[8],address[7]=address[9],address[8]=address[10],address[9]=address[11],address[10]=address[12],address[11]=address[13],out=out2); + RAM4K(in=in,load=c,address[0]=address[2],address[1]=address[3],address[2]=address[4],address[3]=address[5],address[4]=address[6],address[5]=address[7],address[6]=address[8],address[7]=address[9],address[8]=address[10],address[9]=address[11],address[10]=address[12],address[11]=address[13],out=out3); + RAM4K(in=in,load=d,address[0]=address[2],address[1]=address[3],address[2]=address[4],address[3]=address[5],address[4]=address[6],address[5]=address[7],address[6]=address[8],address[7]=address[9],address[8]=address[10],address[9]=address[11],address[10]=address[12],address[11]=address[13],out=out4); + Mux8Way16(a=out1,b=out2,c=out3,d=out4,sel[0]=address[0],sel[1]=address[1],out=out); +} \ No newline at end of file diff --git a/Project 3/RAM4K.hdl b/Project 3/RAM4K.hdl new file mode 100644 index 0000000..63c058a --- /dev/null +++ b/Project 3/RAM4K.hdl @@ -0,0 +1,29 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/03/b/RAM4K.hdl + +/** + * Memory of 4K registers, each 16 bit-wide. Out holds the value + * stored at the memory location specified by address. If load==1, then + * the in value is loaded into the memory location specified by address + * (the loaded value will be emitted to out from the next time step onward). + */ + +CHIP RAM4K { + IN in[16], load, address[12]; + OUT out[16]; + + PARTS: + // Put your code here: + DMux8Way(in=load,sel[0]=address[0],sel[1]=address[1],sel[2]=address[2],a=a,b=b,c=c,d=d,e=e,f=f,g=g,h=h); + RAM512(in=in,load=a,address[0]=address[3],address[1]=address[4],address[2]=address[5],address[3]=address[6],address[4]=address[7],address[5]=address[8],address[6]=address[9],address[7]=address[10],address[8]=address[11],out=out1); + RAM512(in=in,load=b,address[0]=address[3],address[1]=address[4],address[2]=address[5],address[3]=address[6],address[4]=address[7],address[5]=address[8],address[6]=address[9],address[7]=address[10],address[8]=address[11],out=out2); + RAM512(in=in,load=c,address[0]=address[3],address[1]=address[4],address[2]=address[5],address[3]=address[6],address[4]=address[7],address[5]=address[8],address[6]=address[9],address[7]=address[10],address[8]=address[11],out=out3); + RAM512(in=in,load=d,address[0]=address[3],address[1]=address[4],address[2]=address[5],address[3]=address[6],address[4]=address[7],address[5]=address[8],address[6]=address[9],address[7]=address[10],address[8]=address[11],out=out4); + RAM512(in=in,load=e,address[0]=address[3],address[1]=address[4],address[2]=address[5],address[3]=address[6],address[4]=address[7],address[5]=address[8],address[6]=address[9],address[7]=address[10],address[8]=address[11],out=out5); + RAM512(in=in,load=f,address[0]=address[3],address[1]=address[4],address[2]=address[5],address[3]=address[6],address[4]=address[7],address[5]=address[8],address[6]=address[9],address[7]=address[10],address[8]=address[11],out=out6); + RAM512(in=in,load=g,address[0]=address[3],address[1]=address[4],address[2]=address[5],address[3]=address[6],address[4]=address[7],address[5]=address[8],address[6]=address[9],address[7]=address[10],address[8]=address[11],out=out7); + RAM512(in=in,load=h,address[0]=address[3],address[1]=address[4],address[2]=address[5],address[3]=address[6],address[4]=address[7],address[5]=address[8],address[6]=address[9],address[7]=address[10],address[8]=address[11],out=out8); + Mux8Way16(a=out1,b=out2,c=out3,d=out4,e=out5,f=out6,g=out7,h=out8,sel[0]=address[0],sel[1]=address[1],sel[2]=address[2],out=out); +} \ No newline at end of file diff --git a/Project 3/RAM512.hdl b/Project 3/RAM512.hdl new file mode 100644 index 0000000..acac4be --- /dev/null +++ b/Project 3/RAM512.hdl @@ -0,0 +1,29 @@ +// This file is part of the materials accompanying the book +// "The Elements of Computing Systems" by Nisan and Schocken, +// MIT Press. Book site: www.idc.ac.il/tecs +// File name: projects/03/b/RAM512.hdl + +/** + * Memory of 512 registers, each 16 bit-wide. Out holds the value + * stored at the memory location specified by address. If load==1, then + * the in value is loaded into the memory location specified by address + * (the loaded value will be emitted to out from the next time step onward). + */ + +CHIP RAM512 { + IN in[16], load, address[9]; + OUT out[16]; + + PARTS: + // Put your code here: + DMux8Way(in=load,sel[0]=address[0],sel[1]=address[1],sel[2]=address[2],a=a,b=b,c=c,d=d,e=e,f=f,g=g,h=h); + RAM64(in=in,load=a,address[0]=address[3],address[1]=address[4],address[2]=address[5],address[3]=address[6],address[4]=address[7],address[5]=address[8],out=out1); + RAM64(in=in,load=b,address[0]=address[3],address[1]=address[4],address[2]=address[5],address[3]=address[6],address[4]=address[7],address[5]=address[8],out=out2); + RAM64(in=in,load=c,address[0]=address[3],address[1]=address[4],address[2]=address[5],address[3]=address[6],address[4]=address[7],address[5]=address[8],out=out3); + RAM64(in=in,load=d,address[0]=address[3],address[1]=address[4],address[2]=address[5],address[3]=address[6],address[4]=address[7],address[5]=address[8],out=out4); + RAM64(in=in,load=e,address[0]=address[3],address[1]=address[4],address[2]=address[5],address[3]=address[6],address[4]=address[7],address[5]=address[8],out=out5); + RAM64(in=in,load=f,address[0]=address[3],address[1]=address[4],address[2]=address[5],address[3]=address[6],address[4]=address[7],address[5]=address[8],out=out6); + RAM64(in=in,load=g,address[0]=address[3],address[1]=address[4],address[2]=address[5],address[3]=address[6],address[4]=address[7],address[5]=address[8],out=out7); + RAM64(in=in,load=h,address[0]=address[3],address[1]=address[4],address[2]=address[5],address[3]=address[6],address[4]=address[7],address[5]=address[8],out=out8); + Mux8Way16(a=out1,b=out2,c=out3,d=out4,e=out5,f=out6,g=out7,h=out8,sel[0]=address[0],sel[1]=address[1],sel[2]=address[2],out=out); +} \ No newline at end of file diff --git a/Project 3/RAM64.hdl b/Project 3/RAM64.hdl new file mode 100644 index 0000000..1c69cdb --- /dev/null +++ b/Project 3/RAM64.hdl @@ -0,0 +1,31 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/03/a/RAM64.hdl + +/** + * Memory of 64 registers, each 16 bit-wide. Out holds the value + * stored at the memory location specified by address. If load==1, then + * the in value is loaded into the memory location specified by address + * (the loaded value will be emitted to out from the next time step onward). + */ + +CHIP RAM64 { + IN in[16], load, address[6]; + OUT out[16]; + + PARTS: + // Put your code here: + DMux8Way(in=load,sel[0]=address[0],sel[1]=address[1],sel[2]=address[2],a=a,b=b,c=c,d=d,e=e,f=f,g=g,h=h); + RAM8(in=in,load=a,address[0]=address[3],address[1]=address[4],address[2]=address[5],out=out1); + RAM8(in=in,load=b,address[0]=address[3],address[1]=address[4],address[2]=address[5],out=out2); + RAM8(in=in,load=c,address[0]=address[3],address[1]=address[4],address[2]=address[5],out=out3); + RAM8(in=in,load=d,address[0]=address[3],address[1]=address[4],address[2]=address[5],out=out4); + RAM8(in=in,load=e,address[0]=address[3],address[1]=address[4],address[2]=address[5],out=out5); + RAM8(in=in,load=f,address[0]=address[3],address[1]=address[4],address[2]=address[5],out=out6); + RAM8(in=in,load=g,address[0]=address[3],address[1]=address[4],address[2]=address[5],out=out7); + RAM8(in=in,load=h,address[0]=address[3],address[1]=address[4],address[2]=address[5],out=out8); + Mux8Way16(a=out1,b=out2,c=out3,d=out4,e=out5,f=out6,g=out7,h=out8,sel[0]=address[0],sel[1]=address[1],sel[2]=address[2],out=out); + + +} \ No newline at end of file diff --git a/Project 3/RAM8.hdl b/Project 3/RAM8.hdl new file mode 100644 index 0000000..bb8f337 --- /dev/null +++ b/Project 3/RAM8.hdl @@ -0,0 +1,29 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/03/a/RAM8.hdl + +/** + * Memory of 8 registers, each 16 bit-wide. Out holds the value + * stored at the memory location specified by address. If load==1, then + * the in value is loaded into the memory location specified by address + * (the loaded value will be emitted to out from the next time step onward). + */ + +CHIP RAM8 { + IN in[16], load, address[3]; + OUT out[16]; + + PARTS: + // Put your code here: + DMux8Way(in=load,sel=address,a=a,b=b,c=c,d=d,e=e,f=f,g=g,h=h); + Register(in=in,load=a,out=out1); + Register(in=in,load=b,out=out2); + Register(in=in,load=c,out=out3); + Register(in=in,load=d,out=out4); + Register(in=in,load=e,out=out5); + Register(in=in,load=f,out=out6); + Register(in=in,load=g,out=out7); + Register(in=in,load=h,out=out8); + Mux8Way16(a=out1,b=out2,c=out3,d=out4,e=out5,f=out6,g=out7,h=out8,sel=address,out=out); +} \ No newline at end of file diff --git a/Project 3/Register.hdl b/Project 3/Register.hdl new file mode 100644 index 0000000..ab91dfb --- /dev/null +++ b/Project 3/Register.hdl @@ -0,0 +1,34 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/03/a/Register.hdl + +/** + * 16-bit register: + * If load[t] == 1 then out[t+1] = in[t] + * else out does not change + */ + +CHIP Register { + IN in[16], load; + OUT out[16]; + + PARTS: + // Put your code here: + Bit(in=in[0],load=load,out=out[0]); + Bit(in=in[1],load=load,out=out[1]); + Bit(in=in[2],load=load,out=out[2]); + Bit(in=in[3],load=load,out=out[3]); + Bit(in=in[4],load=load,out=out[4]); + Bit(in=in[5],load=load,out=out[5]); + Bit(in=in[6],load=load,out=out[6]); + Bit(in=in[7],load=load,out=out[7]); + Bit(in=in[8],load=load,out=out[8]); + Bit(in=in[9],load=load,out=out[9]); + Bit(in=in[10],load=load,out=out[10]); + Bit(in=in[11],load=load,out=out[11]); + Bit(in=in[12],load=load,out=out[12]); + Bit(in=in[13],load=load,out=out[13]); + Bit(in=in[14],load=load,out=out[14]); + Bit(in=in[15],load=load,out=out[15]); +} \ No newline at end of file diff --git a/Project 4/Fill.asm b/Project 4/Fill.asm new file mode 100644 index 0000000..748b479 --- /dev/null +++ b/Project 4/Fill.asm @@ -0,0 +1,59 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/04/Fill.asm + +// Runs an infinite loop that listens to the keyboard input. +// When a key is pressed (any key), the program blackens the screen, +// i.e. writes "black" in every pixel; +// the screen should remain fully black as long as the key is pressed. +// When no key is pressed, the program clears the screen, i.e. writes +// "white" in every pixel; +// the screen should remain fully clear as long as no key is pressed. + +// Put your code here. +(LOOP) + @R1 + M=0 + @KBD + D=M + @BLACK + D;JGT + @WHITE + D;JEQ +(BLACK) + @SCREEN + D=M + @LOOP + D;JLT + (BLACKLOOP) + @R1 + D=M + M=M+1 + @SCREEN + AD=D+A + M=-1 + @24575 + D=D-A + @LOOP + D;JEQ + @BLACKLOOP + 0;JMP +(WHITE) + @SCREEN + D=M + @LOOP + D;JEQ + (WHITELOOP) + @R1 + D=M + M=M+1 + @SCREEN + AD=D+A + M=0 + @24575 + D=D-A + @LOOP + D;JEQ + @WHITELOOP + 0;JMP \ No newline at end of file diff --git a/Project 4/Mult.asm b/Project 4/Mult.asm new file mode 100644 index 0000000..298e4a9 --- /dev/null +++ b/Project 4/Mult.asm @@ -0,0 +1,26 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/04/Mult.asm + +// Multiplies R0 and R1 and stores the result in R2. +// (R0, R1, R2 refer to RAM[0], RAM[1], and RAM[2], respectively.) + +// Put your code here. + @R2 + M=0 +(LOOP) + @R0 + D=M + @END + D;JLE + @R0 + M=M-1 + @R1 + D=M + @R2 + M=D+M + @LOOP + 0;JMP +(END) + @END \ No newline at end of file diff --git a/Project 5/CPU.hdl b/Project 5/CPU.hdl new file mode 100644 index 0000000..cf27973 --- /dev/null +++ b/Project 5/CPU.hdl @@ -0,0 +1,67 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/05/CPU.hdl + +/** + * The Hack CPU (Central Processing unit), consisting of an ALU, + * two registers named A and D, and a program counter named PC. + * The CPU is designed to fetch and execute instructions written in + * the Hack machine language. In particular, functions as follows: + * Executes the inputted instruction according to the Hack machine + * language specification. The D and A in the language specification + * refer to CPU-resident registers, while M refers to the external + * memory location addressed by A, i.e. to Memory[A]. The inM input + * holds the value of this location. If the current instruction needs + * to write a value to M, the value is placed in outM, the address + * of the target location is placed in the addressM output, and the + * writeM control bit is asserted. (When writeM==0, any value may + * appear in outM). The outM and writeM outputs are combinational: + * they are affected instantaneously by the execution of the current + * instruction. The addressM and pc outputs are clocked: although they + * are affected by the execution of the current instruction, they commit + * to their new values only in the next time step. If reset==1 then the + * CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather + * than to the address resulting from executing the current instruction. + */ + +CHIP CPU { + + IN inM[16], // M value input (M = contents of RAM[A]) + instruction[16], // Instruction for execution + reset; // Signals whether to re-start the current + // program (reset==1) or continue executing + // the current program (reset==0). + + OUT outM[16], // M value output + writeM, // Write to M? + addressM[15], // Address in data memory (of M) + pc[15]; // address of next instruction + + PARTS: + // Put your code here: + Not(in=instruction[15],out=negI); + Mux16(a=ALUResult,b=instruction,sel=negI,out=instructorMux); + Or(a=negI,b=instruction[5],out=ARegLoad); + And(a=instruction[4],b=instruction[15],out=DRegLoad); + And(a=instruction[15],b=instruction[3],out=writeM); + ARegister(in=instructorMux,load=ARegLoad,out=ARegOut,out[0..14]=addressM); + Mux16(a=ARegOut,b=inM,sel=instruction[12],out=inputMux); + DRegister(in=ALUResult,load=DRegLoad,out=DRegOut); + ALU(x=DRegOut,y=inputMux,zx=instruction[11],nx=instruction[10],zy=instruction[9],ny=instruction[8],f=instruction[7],no=instruction[6],out=ALUResult,out=outM,ng=ng,zr=zr); + + Not(in=ng,out=negng); + Not(in=zr,out=negzr); + And(a=instruction[2],b=ng,out=jmp1); + And(a=instruction[1],b=zr,out=jmp2); + And(a=instruction[0],b=negng,out=jmp31); + And(a=jmp31,b=negzr,out=jmp3); + Or(a=jmp1,b=jmp2,out=jmp4); + Or(a=jmp3,b=jmp4,out=jmp5); + And(a=jmp5,b=instruction[15],out=jmp); + + PC(in=ARegOut,reset=reset,load=jmp,inc=true,out[0..14]=pc); + + + +} \ No newline at end of file diff --git a/Project 5/Computer.hdl b/Project 5/Computer.hdl new file mode 100644 index 0000000..d4c1e24 --- /dev/null +++ b/Project 5/Computer.hdl @@ -0,0 +1,26 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/05/Computer.hdl + +/** + * The HACK computer, including CPU, ROM and RAM. + * When reset is 0, the program stored in the computer's ROM executes. + * When reset is 1, the execution of the program restarts. + * Thus, to start a program's execution, reset must be pushed "up" (1) + * and "down" (0). From this point onward the user is at the mercy of + * the software. In particular, depending on the program's code, the + * screen may show some output and the user may be able to interact + * with the computer via the keyboard. + */ + +CHIP Computer { + + IN reset; + + PARTS: + // Put your code here: + ROM32K(address=pc,out=instruction); + CPU(instruction=instruction,reset=reset,inM=inM,pc=pc,addressM=addressM,outM=outM,writeM=writeM); + Memory(in=outM,load=writeM,address=addressM,out=inM); +} \ No newline at end of file diff --git a/Project 5/Memory.hdl b/Project 5/Memory.hdl new file mode 100644 index 0000000..e287ad1 --- /dev/null +++ b/Project 5/Memory.hdl @@ -0,0 +1,38 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/05/Memory.hdl + +/** + * The complete address space of the Hack computer's memory, + * including RAM and memory-mapped I/O. + * The chip facilitates read and write operations, as follows: + * Read: out(t) = Memory[address(t)](t) + * Write: if load(t-1) then Memory[address(t-1)](t) = in(t-1) + * In words: the chip always outputs the value stored at the memory + * location specified by address. If load==1, the in value is loaded + * into the memory location specified by address. This value becomes + * available through the out output from the next time step onward. + * Address space rules: + * Only the upper 16K+8K+1 words of the Memory chip are used. + * Access to address>0x6000 is invalid. Access to any address in + * the range 0x4000-0x5FFF results in accessing the screen memory + * map. Access to address 0x6000 results in accessing the keyboard + * memory map. The behavior in these addresses is described in the + * Screen and Keyboard chip specifications given in the book. + */ + +CHIP Memory { + IN in[16], load, address[15]; + OUT out[16]; + + PARTS: + // Put your code here: + DMux(in=load,sel=address[14],a=a,b=b); + DMux(in=b,sel=address[13],a=c,b=d); + RAM16K(in=in,load=a,address[0..13]=address[0..13],out=out1); + Screen(in=in,load=c,address[0..12]=address[0..12],out=out2); + Keyboard(out=out3); + Mux16(a=out2,b=out3,sel=address[13],out=out4); + Mux16(a=out1,b=out4,sel=address[14],out=out); +} \ No newline at end of file