// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/05/CPU.hdl

/**
 * The Hack CPU (Central Processing unit), consisting of an ALU,
 * two registers named A and D, and a program counter named PC.
 * The CPU is designed to fetch and execute instructions written in 
 * the Hack machine language. In particular, functions as follows:
 * Executes the inputted instruction according to the Hack machine 
 * language specification. The D and A in the language specification
 * refer to CPU-resident registers, while M refers to the external
 * memory location addressed by A, i.e. to Memory[A]. The inM input 
 * holds the value of this location. If the current instruction needs 
 * to write a value to M, the value is placed in outM, the address 
 * of the target location is placed in the addressM output, and the 
 * writeM control bit is asserted. (When writeM==0, any value may 
 * appear in outM). The outM and writeM outputs are combinational: 
 * they are affected instantaneously by the execution of the current 
 * instruction. The addressM and pc outputs are clocked: although they 
 * are affected by the execution of the current instruction, they commit 
 * to their new values only in the next time step. If reset==1 then the 
 * CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather 
 * than to the address resulting from executing the current instruction. 
 */

CHIP CPU {

    IN  inM[16],         // M value input  (M = contents of RAM[A])
        instruction[16], // Instruction for execution
        reset;           // Signals whether to re-start the current
                         // program (reset==1) or continue executing
                         // the current program (reset==0).

    OUT outM[16],        // M value output
        writeM,          // Write to M? 
        addressM[15],    // Address in data memory (of M)
        pc[15];          // address of next instruction

    PARTS:
    // Put your code here:
    Not(in=instruction[15],out=negI);
    Mux16(a=ALUResult,b=instruction,sel=negI,out=instructorMux);
    Or(a=negI,b=instruction[5],out=ARegLoad);
    And(a=instruction[4],b=instruction[15],out=DRegLoad);
    And(a=instruction[15],b=instruction[3],out=writeM);
    ARegister(in=instructorMux,load=ARegLoad,out=ARegOut,out[0..14]=addressM);
    Mux16(a=ARegOut,b=inM,sel=instruction[12],out=inputMux);
    DRegister(in=ALUResult,load=DRegLoad,out=DRegOut);
    ALU(x=DRegOut,y=inputMux,zx=instruction[11],nx=instruction[10],zy=instruction[9],ny=instruction[8],f=instruction[7],no=instruction[6],out=ALUResult,out=outM,ng=ng,zr=zr);
    
    Not(in=ng,out=negng);
    Not(in=zr,out=negzr);
    And(a=instruction[2],b=ng,out=jmp1);
    And(a=instruction[1],b=zr,out=jmp2);
    And(a=instruction[0],b=negng,out=jmp31);
    And(a=jmp31,b=negzr,out=jmp3);
    Or(a=jmp1,b=jmp2,out=jmp4);
    Or(a=jmp3,b=jmp4,out=jmp5);
    And(a=jmp5,b=instruction[15],out=jmp);

    PC(in=ARegOut,reset=reset,load=jmp,inc=true,out[0..14]=pc);


    
}