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Changed to a Unix file structure

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This commit is contained in:
Daniel Cujba
2023-03-08 08:39:43 +02:00
parent bf424a2436
commit ec70594b6d
35 changed files with 33430 additions and 33430 deletions
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Source/Logic_Gates/And16.py
+11 -11
View File
@@ -1,12 +1,12 @@
from Source.Pre_Built_Gates.And import And
from Source.Pre_Built_Gates.Power import Power
class And16:
def __init__(self,a,b) -> None:
self.a=a
self.b=b
self.out=[Power(False) for _ in range(16)]
self()
def __call__(self) -> None:
for i in range(16):
from Source.Pre_Built_Gates.And import And
from Source.Pre_Built_Gates.Power import Power
class And16:
def __init__(self,a,b) -> None:
self.a=a
self.b=b
self.out=[Power(False) for _ in range(16)]
self()
def __call__(self) -> None:
for i in range(16):
self.out[i].out=And(self.a.out[i],self.b.out[i]).out
Source/Logic_Gates/DMux.py
+15 -15
View File
@@ -1,16 +1,16 @@
from Source.Pre_Built_Gates.And import And
from Source.Pre_Built_Gates.Not import Not
from Source.Pre_Built_Gates.Power import Power
class DMux:
def __init__(self,a,sel) -> None:
self.a=a
self.sel=sel
self.out=[Power(False),Power(False)]
self()
def __call__(self) -> None:
negSel=Not(self.sel)
out1=And(self.a,negSel)
out2=And(self.a,self.sel)
self.out[0].out=out1.out
from Source.Pre_Built_Gates.And import And
from Source.Pre_Built_Gates.Not import Not
from Source.Pre_Built_Gates.Power import Power
class DMux:
def __init__(self,a,sel) -> None:
self.a=a
self.sel=sel
self.out=[Power(False),Power(False)]
self()
def __call__(self) -> None:
negSel=Not(self.sel)
out1=And(self.a,negSel)
out2=And(self.a,self.sel)
self.out[0].out=out1.out
self.out[1].out=out2.out
Source/Logic_Gates/DMux8Way.py
+24 -24
View File
@@ -1,25 +1,25 @@
from Source.Logic_Gates.DMux import DMux
from Source.Pre_Built_Gates.Power import Power
class DMux8Way:
def __init__(self,a,sel) -> None:
self.a=a
self.sel=sel
self.out=[Power(False) for _ in range(8)]
self()
def __call__(self):
dmux1=DMux(self.a,self.sel.out[0])
dmux2=DMux(dmux1.out[0],self.sel.out[1])
dmux3=DMux(dmux1.out[1],self.sel.out[1])
dmux4=DMux(dmux2.out[0],self.sel.out[2])
dmux5=DMux(dmux2.out[1],self.sel.out[2])
dmux6=DMux(dmux3.out[0],self.sel.out[2])
dmux7=DMux(dmux3.out[1],self.sel.out[2])
self.out[0].out=dmux4.out[0].out
self.out[1].out=dmux4.out[1].out
self.out[2].out=dmux5.out[0].out
self.out[3].out=dmux5.out[1].out
self.out[4].out=dmux6.out[0].out
self.out[5].out=dmux6.out[1].out
self.out[6].out=dmux7.out[0].out
from Source.Logic_Gates.DMux import DMux
from Source.Pre_Built_Gates.Power import Power
class DMux8Way:
def __init__(self,a,sel) -> None:
self.a=a
self.sel=sel
self.out=[Power(False) for _ in range(8)]
self()
def __call__(self):
dmux1=DMux(self.a,self.sel.out[0])
dmux2=DMux(dmux1.out[0],self.sel.out[1])
dmux3=DMux(dmux1.out[1],self.sel.out[1])
dmux4=DMux(dmux2.out[0],self.sel.out[2])
dmux5=DMux(dmux2.out[1],self.sel.out[2])
dmux6=DMux(dmux3.out[0],self.sel.out[2])
dmux7=DMux(dmux3.out[1],self.sel.out[2])
self.out[0].out=dmux4.out[0].out
self.out[1].out=dmux4.out[1].out
self.out[2].out=dmux5.out[0].out
self.out[3].out=dmux5.out[1].out
self.out[4].out=dmux6.out[0].out
self.out[5].out=dmux6.out[1].out
self.out[6].out=dmux7.out[0].out
self.out[7].out=dmux7.out[1].out
Source/Logic_Gates/Mux.py
+16 -16
View File
@@ -1,17 +1,17 @@
from Source.Pre_Built_Gates.And import And
from Source.Pre_Built_Gates.Not import Not
from Source.Pre_Built_Gates.Or import Or
class Mux:
def __init__(self,a,b,sel) -> None:
self.a=a
self.b=b
self.sel=sel
self.out=None
self()
def __call__(self) -> None:
negSel=Not(self.sel)
out1=And(self.a,negSel)
out2=And(self.b,self.sel)
out3=Or(out1,out2)
from Source.Pre_Built_Gates.And import And
from Source.Pre_Built_Gates.Not import Not
from Source.Pre_Built_Gates.Or import Or
class Mux:
def __init__(self,a,b,sel) -> None:
self.a=a
self.b=b
self.sel=sel
self.out=None
self()
def __call__(self) -> None:
negSel=Not(self.sel)
out1=And(self.a,negSel)
out2=And(self.b,self.sel)
out3=Or(out1,out2)
self.out=out3.out
Source/Logic_Gates/Mux16.py
+11 -11
View File
@@ -1,12 +1,12 @@
from Source.Logic_Gates.Mux import Mux
from Source.Pre_Built_Gates.Power import Power
class Mux16:
def __init__(self,a,b,sel) -> None:
self.a=a
self.b=b
self.sel=sel
self.out=[Power(False) for _ in range(16)]
self()
def __call__(self) -> None:
for i in range(16):
from Source.Logic_Gates.Mux import Mux
from Source.Pre_Built_Gates.Power import Power
class Mux16:
def __init__(self,a,b,sel) -> None:
self.a=a
self.b=b
self.sel=sel
self.out=[Power(False) for _ in range(16)]
self()
def __call__(self) -> None:
for i in range(16):
self.out[i].out=Mux(self.a.out[i],self.b.out[i],self.sel).out
Source/Logic_Gates/Mux8Way16.py
+25 -25
View File
@@ -1,26 +1,26 @@
from Source.Logic_Gates.Mux16 import Mux16
from Source.Pre_Built_Gates.Power import Power
class Mux8Way16:
def __init__(self,a,b,c,d,e,f,g,h,sel) -> None:
self.a=a
self.b=b
self.c=c
self.d=d
self.e=e
self.f=f
self.g=g
self.h=h
self.sel=sel
self.out=[Power(False) for _ in range(16)]
self()
def __call__(self):
mux1=Mux16(self.a,self.b,self.sel.out[2])
mux2=Mux16(self.c,self.d,self.sel.out[2])
mux3=Mux16(self.e,self.f,self.sel.out[2])
mux4=Mux16(self.g,self.h,self.sel.out[2])
mux5=Mux16(mux1,mux2,self.sel.out[1])
mux6=Mux16(mux3,mux4,self.sel.out[1])
mux7=Mux16(mux5,mux6,self.sel.out[0])
for i in range(16):
from Source.Logic_Gates.Mux16 import Mux16
from Source.Pre_Built_Gates.Power import Power
class Mux8Way16:
def __init__(self,a,b,c,d,e,f,g,h,sel) -> None:
self.a=a
self.b=b
self.c=c
self.d=d
self.e=e
self.f=f
self.g=g
self.h=h
self.sel=sel
self.out=[Power(False) for _ in range(16)]
self()
def __call__(self):
mux1=Mux16(self.a,self.b,self.sel.out[2])
mux2=Mux16(self.c,self.d,self.sel.out[2])
mux3=Mux16(self.e,self.f,self.sel.out[2])
mux4=Mux16(self.g,self.h,self.sel.out[2])
mux5=Mux16(mux1,mux2,self.sel.out[1])
mux6=Mux16(mux3,mux4,self.sel.out[1])
mux7=Mux16(mux5,mux6,self.sel.out[0])
for i in range(16):
self.out[i].out=mux7.out[i].out
Source/Logic_Gates/Nand.py
+13 -13
View File
@@ -1,13 +1,13 @@
from Source.Pre_Built_Gates.Not import Not
from Source.Pre_Built_Gates.And import And
class Nand:
def __init__(self,a,b) -> None:
self.a=a
self.b=b
self.out=None
self()
def __call__(self) -> None:
out1=And(self.a,self.b)
out2=Not(out1)
self.out=out2.out
from Source.Pre_Built_Gates.Not import Not
from Source.Pre_Built_Gates.And import And
class Nand:
def __init__(self,a,b) -> None:
self.a=a
self.b=b
self.out=None
self()
def __call__(self) -> None:
out1=And(self.a,self.b)
out2=Not(out1)
self.out=out2.out
Source/Logic_Gates/Not16.py
+10 -10
View File
@@ -1,11 +1,11 @@
from Source.Pre_Built_Gates.Not import Not
from Source.Pre_Built_Gates.Power import Power
class Not16:
def __init__(self,a) -> None:
self.a=a
self.out=[Power(False) for _ in range(16)]
self()
def __call__(self) -> None:
for i in range(16):
from Source.Pre_Built_Gates.Not import Not
from Source.Pre_Built_Gates.Power import Power
class Not16:
def __init__(self,a) -> None:
self.a=a
self.out=[Power(False) for _ in range(16)]
self()
def __call__(self) -> None:
for i in range(16):
self.out[i].out=Not(self.a.out[i]).out
Source/Logic_Gates/Or16.py
+11 -11
View File
@@ -1,12 +1,12 @@
from Source.Pre_Built_Gates.Or import Or
from Source.Pre_Built_Gates.Power import Power
class Or16:
def __init__(self,a,b) -> None:
self.a=a
self.b=b
self.out=[Power(False) for _ in range(16)]
self()
def __call__(self) -> None:
for i in range(16):
from Source.Pre_Built_Gates.Or import Or
from Source.Pre_Built_Gates.Power import Power
class Or16:
def __init__(self,a,b) -> None:
self.a=a
self.b=b
self.out=[Power(False) for _ in range(16)]
self()
def __call__(self) -> None:
for i in range(16):
self.out[i].out=Or(self.a.out[i],self.b.out[i]).out
Source/Logic_Gates/Or8Way.py
+16 -16
View File
@@ -1,16 +1,16 @@
from Source.Pre_Built_Gates.Or import Or
class Or8Way:
def __init__(self,a) -> None:
self.a=a
self.out=None
self()
def __call__(self) -> None:
or1=Or(self.a.out[0],self.a.out[1])
or2=Or(self.a.out[2],self.a.out[3])
or3=Or(self.a.out[4],self.a.out[5])
or4=Or(self.a.out[6],self.a.out[7])
or5=Or(or1,or2)
or6=Or(or3,or4)
or7=Or(or5,or6)
self.out=or7.out
from Source.Pre_Built_Gates.Or import Or
class Or8Way:
def __init__(self,a) -> None:
self.a=a
self.out=None
self()
def __call__(self) -> None:
or1=Or(self.a.out[0],self.a.out[1])
or2=Or(self.a.out[2],self.a.out[3])
or3=Or(self.a.out[4],self.a.out[5])
or4=Or(self.a.out[6],self.a.out[7])
or5=Or(or1,or2)
or6=Or(or3,or4)
or7=Or(or5,or6)
self.out=or7.out
Source/Logic_Gates/Xor.py
+14 -14
View File
@@ -1,15 +1,15 @@
from Source.Pre_Built_Gates.Or import Or
from Source.Pre_Built_Gates.And import And
from Source.Logic_Gates.Nand import Nand
class Xor:
def __init__(self,a,b) -> None:
self.a=a
self.b=b
self.out=None
self()
def __call__(self) -> None:
out1=Or(self.a,self.b)
out2=Nand(self.a,self.b)
out3=And(out1,out2)
from Source.Pre_Built_Gates.Or import Or
from Source.Pre_Built_Gates.And import And
from Source.Logic_Gates.Nand import Nand
class Xor:
def __init__(self,a,b) -> None:
self.a=a
self.b=b
self.out=None
self()
def __call__(self) -> None:
out1=Or(self.a,self.b)
out2=Nand(self.a,self.b)
out3=And(out1,out2)
self.out=out3.out