Initial Commit

Source/Components/Boolean_Arithmetic/ALU.py

@@ -0,0 +1,42 @@
+from Source.Pre_Built_Gates.Power import Power
+from Source.Logic_Gates.Mux16 import Mux16
+from Source.Logic_Gates.Not16 import Not16
+from Source.Logic_Gates.And16 import And16
+from Source.Components.Boolean_Arithmetic.Add16 import Add16
+from Source.Logic_Gates.Or8Way import Or8Way
+from Source.Pre_Built_Gates.Or import Or
+from Source.Pre_Built_Gates.And import And
+from Source.Pre_Built_Gates.Not import Not
+
+class ALU:
+    def __init__(self,x,y,zx,nx,zy,ny,f,no) -> None:
+        self.x=x
+        self.y=y
+        self.zx=zx
+        self.nx=nx
+        self.zy=zy
+        self.ny=ny
+        self.f=f
+        self.no=no
+        self.out=[Power([Power(False) for _ in range(16)]),Power(False),Power(False)]
+        self()
+    def __call__(self) -> None:
+        x1=Mux16(self.x,Power([Power(False) for _ in range(16)]),self.zx)
+        y1=Mux16(self.y,Power([Power(False) for _ in range(16)]),self.zy)
+        notx1=Not16(x1)
+        noty1=Not16(y1)
+        x2=Mux16(x1,notx1,self.nx)
+        y2=Mux16(y1,noty1,self.ny)
+        addout=Add16(x2,y2)
+        andout=And16(x2,y2)
+        fout=Mux16(andout,addout,self.f)
+        notfout=Not16(fout)
+        out1=Mux16(fout,notfout,self.no)
+        zr1=Or8Way(Power(out1.out[0:8]))
+        zr2=Or8Way(Power(out1.out[8:16]))
+        zr3=Or(zr1,zr2)
+        zr=Not(zr3)
+        for i in range(16):
+            self.out[0].out[i].out=out1.out[i].out
+        self.out[1].out=zr.out
+        self.out[2].out=out1.out[0].out

Source/Components/Boolean_Arithmetic/Add16.py

@@ -0,0 +1,44 @@
+from Source.Components.Boolean_Arithmetic.FullAdder import FullAdder
+from Source.Components.Boolean_Arithmetic.HalfAdder import HalfAdder
+from Source.Pre_Built_Gates.Power import Power
+
+class Add16:
+    def __init__(self,a,b) -> None:
+        self.a=a
+        self.b=b
+        self.out=[Power(False) for _ in range(16)]
+        self()
+    def __call__(self) -> None:
+        add1=HalfAdder(self.a.out[15],self.b.out[15])
+        add2=FullAdder(self.a.out[14],self.b.out[14],add1.out[1])
+        add3=FullAdder(self.a.out[13],self.b.out[13],add2.out[1])
+        add4=FullAdder(self.a.out[12],self.b.out[12],add3.out[1])
+        add5=FullAdder(self.a.out[11],self.b.out[11],add4.out[1])
+        add6=FullAdder(self.a.out[10],self.b.out[10],add5.out[1])
+        add7=FullAdder(self.a.out[9],self.b.out[9],add6.out[1])
+        add8=FullAdder(self.a.out[8],self.b.out[8],add7.out[1])
+        add9=FullAdder(self.a.out[7],self.b.out[7],add8.out[1])
+        add10=FullAdder(self.a.out[6],self.b.out[6],add9.out[1])
+        add11=FullAdder(self.a.out[5],self.b.out[5],add10.out[1])
+        add12=FullAdder(self.a.out[4],self.b.out[4],add11.out[1])
+        add13=FullAdder(self.a.out[3],self.b.out[3],add12.out[1])
+        add14=FullAdder(self.a.out[2],self.b.out[2],add13.out[1])
+        add15=FullAdder(self.a.out[1],self.b.out[1],add14.out[1])
+        add16=FullAdder(self.a.out[0],self.b.out[0],add15.out[1])
+        
+        self.out[0].out=add16.out[0].out
+        self.out[1].out=add15.out[0].out
+        self.out[2].out=add14.out[0].out
+        self.out[3].out=add13.out[0].out
+        self.out[4].out=add12.out[0].out
+        self.out[5].out=add11.out[0].out
+        self.out[6].out=add10.out[0].out
+        self.out[7].out=add9.out[0].out
+        self.out[8].out=add8.out[0].out
+        self.out[9].out=add7.out[0].out
+        self.out[10].out=add6.out[0].out
+        self.out[11].out=add5.out[0].out
+        self.out[12].out=add4.out[0].out
+        self.out[13].out=add3.out[0].out
+        self.out[14].out=add2.out[0].out
+        self.out[15].out=add1.out[0].out

Source/Components/Boolean_Arithmetic/FullAdder.py

@@ -0,0 +1,17 @@
+from Source.Components.Boolean_Arithmetic.HalfAdder import HalfAdder
+from Source.Logic_Gates.Xor import Xor
+from Source.Pre_Built_Gates.Power import Power
+
+class FullAdder:
+    def __init__(self,a,b,c) -> None:
+        self.a=a
+        self.b=b
+        self.c=c
+        self.out=[Power(False),Power(False)]
+        self()
+    def __call__(self) -> None:
+        ha1=HalfAdder(self.a,self.b)
+        ha2=HalfAdder(ha1.out[0],self.c)
+        xor=Xor(ha1.out[1],ha2.out[1])
+        self.out[0].out=ha2.out[0].out
+        self.out[1].out=xor.out

Source/Components/Boolean_Arithmetic/HalfAdder.py

@@ -0,0 +1,15 @@
+from Source.Pre_Built_Gates.And import And
+from Source.Logic_Gates.Xor import Xor
+from Source.Pre_Built_Gates.Power import Power
+
+class HalfAdder:
+    def __init__(self,a,b) -> None:
+        self.a=a
+        self.b=b
+        self.out=[Power(False),Power(False)]
+        self()
+    def __call__(self) -> None:
+        bit_sum=Xor(self.a,self.b)
+        carry=And(self.a,self.b)
+        self.out[0].out=bit_sum.out
+        self.out[1].out=carry.out

Source/Components/Boolean_Arithmetic/Inc16.py

@@ -0,0 +1,42 @@
+from Source.Pre_Built_Gates.Power import Power
+from Source.Components.Boolean_Arithmetic.HalfAdder import HalfAdder
+
+class Inc16:
+    def __init__(self,a) -> None:
+        self.a=a
+        self.out=[Power(False) for _ in range(16)]
+        self()
+    def __call__(self) -> None:
+        add1=HalfAdder(self.a.out[15],Power(True))
+        add2=HalfAdder(self.a.out[14],add1.out[1])
+        add3=HalfAdder(self.a.out[13],add2.out[1])
+        add4=HalfAdder(self.a.out[12],add3.out[1])
+        add5=HalfAdder(self.a.out[11],add4.out[1])
+        add6=HalfAdder(self.a.out[10],add5.out[1])
+        add7=HalfAdder(self.a.out[9],add6.out[1])
+        add8=HalfAdder(self.a.out[8],add7.out[1])
+        add9=HalfAdder(self.a.out[7],add8.out[1])
+        add10=HalfAdder(self.a.out[6],add9.out[1])
+        add11=HalfAdder(self.a.out[5],add10.out[1])
+        add12=HalfAdder(self.a.out[4],add11.out[1])
+        add13=HalfAdder(self.a.out[3],add12.out[1])
+        add14=HalfAdder(self.a.out[2],add13.out[1])
+        add15=HalfAdder(self.a.out[1],add14.out[1])
+        add16=HalfAdder(self.a.out[0],add15.out[1])
+
+        self.out[0].out=add16.out[0].out
+        self.out[1].out=add15.out[0].out
+        self.out[2].out=add14.out[0].out
+        self.out[3].out=add13.out[0].out
+        self.out[4].out=add12.out[0].out
+        self.out[5].out=add11.out[0].out
+        self.out[6].out=add10.out[0].out
+        self.out[7].out=add9.out[0].out
+        self.out[8].out=add8.out[0].out
+        self.out[9].out=add7.out[0].out
+        self.out[10].out=add6.out[0].out
+        self.out[11].out=add5.out[0].out
+        self.out[12].out=add4.out[0].out
+        self.out[13].out=add3.out[0].out
+        self.out[14].out=add2.out[0].out
+        self.out[15].out=add1.out[0].out

Source/Components/CPU.py

@@ -0,0 +1,60 @@
+from Source.Pre_Built_Gates.Not import Not
+from Source.Pre_Built_Gates.And import And
+from Source.Pre_Built_Gates.Or import Or
+from Source.Pre_Built_Gates.Power import Power
+from Source.Logic_Gates.Mux16 import Mux16
+from Source.Components.Boolean_Arithmetic.ALU import ALU
+from Source.Components.Sequential_Logic.Register import Register
+from Source.Components.Sequential_Logic.PC import PC
+
+class CPU:
+    def __init__(self,inM,instruction,reset) -> None:
+        self.inM=inM
+        self.instruction=instruction
+        self.reset=reset
+        self.out=[Power([Power(False) for _ in range(16)]),Power(False),Power([Power(False) for _ in range(15)]),Power([Power(False) for _ in range(15)])]
+        self.mux=Power([Power(False) for _ in range(16)])
+        self.ALUout=Power([Power(False) for _ in range(16)])
+        self.a_load=Power(False)
+        self.d_load=Power(False)
+        self.PC_load=Power(False)
+        self.A_register=Register(self.mux,self.a_load)
+        self.D_register=Register(self.ALUout,self.d_load)
+        self.PC=PC(self.A_register,self.PC_load,Power(True),self.reset)
+        self()
+    def __call__(self) -> None:
+        not1=Not(self.instruction.out[0])
+        mux1=Mux16(self.ALUout,self.instruction,not1)
+        for i in range(16):
+            self.mux.out[i].out=mux1.out[i].out
+        a_load=Or(not1,self.instruction.out[10])
+        self.a_load.out=a_load.out
+        self.A_register()
+        and1=And(self.instruction.out[0],self.instruction.out[3])
+        mux2=Mux16(self.A_register,self.inM,and1)
+        d_load=And(self.instruction.out[0],self.instruction.out[11])
+        self.d_load.out=d_load.out
+        alu=ALU(self.D_register,mux2,self.instruction.out[4],self.instruction.out[5],self.instruction.out[6],self.instruction.out[7],self.instruction.out[8],self.instruction.out[9])
+        for i in range(16):
+            self.ALUout.out[i].out=alu.out[0].out[i].out
+        self.D_register()
+        and3=And(self.instruction.out[0],self.instruction.out[12])
+        poz=Not(alu.out[2])
+        non_zero=Not(alu.out[1])
+        jgt=And(self.instruction.out[0],self.instruction.out[15])
+        poz_non_zero=And(poz,non_zero)
+        jmp1=And(jgt,poz_non_zero)
+        jeq=And(self.instruction.out[0],self.instruction.out[14])
+        jmp2=And(jeq,alu.out[1])
+        jlt=And(self.instruction.out[0],self.instruction.out[13])
+        jmp3=And(jlt,alu.out[2])
+        jmp4=Or(jmp1,jmp2)
+        jmp5=Or(jmp4,jmp3)
+        self.PC_load.out=jmp5.out
+        self.PC()
+        for i in range(16):
+            self.out[0].out[i].out=alu.out[0].out[i].out
+        self.out[1].out=and3.out
+        for i in range(15):
+            self.out[2].out[i].out=self.A_register.out[i+1].out
+            self.out[3].out[i].out=self.PC.out[i+1].out

Source/Components/Memory.py

@@ -0,0 +1,14 @@
+from Source.Components.Sequential_Logic.RAM32K import RAM32K
+
+class Memory(RAM32K):
+    def log_memory(self):
+        f=open("Source/RAM_Log.txt","w")
+        for a in range(8):
+            for b in range(8):
+                for c in range(8):
+                    for d in range(8):
+                        for e in range(8):
+                            string="".join([str((int(self.ram.out[a].ram.out[b].ram.out[c].ram.out[d].registers.out[e].out[i].out))) for i in range(16)])
+                            string=string+" "+str(int(string[1:16],2) if string[0]=="0" else int(string[1:16],2)-32768)+"\n"
+                            f.write(string)
+        f.close()

Source/Components/ROM32K.py

@@ -0,0 +1,25 @@
+from Source.Pre_Built_Gates.Power import Power
+
+class ROM32K:
+    def __init__(self,a,file_path) -> None:
+        self.a=a
+        self.file_path=file_path
+        self.out=[Power(False) for _ in range(16)]
+        self.memory=[]
+        self.loadROM(self.file_path)
+        self()
+    def __call__(self) -> None:
+        instuction=self.memory[self.bool_to_int(self.a)]
+        for i in range(16):
+            self.out[i].out=instuction[i]
+    def loadROM(self,file_path):
+        f=open(file_path,"r")
+        for _ in range(32768):
+            line=f.readline()
+            self.memory.append([line[j]=="1" for j in range(16)])
+        f.close()
+    def bool_to_int(self,a):
+        x=0
+        for i in range(14,-1,-1):
+            x+=a.out[i].out*(2**(14-i))
+        return x

Source/Components/Sequential_Logic/Bit.py

@@ -0,0 +1,16 @@
+from Source.Pre_Built_Gates.FlipFlop import FlipFlop
+from Source.Logic_Gates.Mux import Mux
+
+class Bit:
+    def __init__(self,a,load) -> None:
+        self.a=a
+        self.load=load
+        self.out=None
+        self.mux=Mux(self,self.a,self.load)
+        self.flipflop=FlipFlop(self.mux)
+        self()
+    def __call__(self) -> None:
+        self.mux()
+        self.flipflop()
+        self.out=self.mux.out
+

Source/Components/Sequential_Logic/PC.py

@@ -0,0 +1,25 @@
+from Source.Logic_Gates.Mux16 import Mux16
+from Source.Components.Boolean_Arithmetic.Inc16 import Inc16
+from Source.Components.Sequential_Logic.Register import Register
+from Source.Pre_Built_Gates.Power import Power
+
+class PC:
+    def __init__(self,a,load,inc,reset) -> None:
+        self.a=a
+        self.load=load
+        self.inc=inc
+        self.reset=reset
+        self.out=[Power(False) for _ in range(16)]
+        self.mux3=Power([Power(False) for _ in range(16)])
+        self.register=Register(self.mux3,Power(True))
+        self()
+    def __call__(self) -> None:
+        inc1=Inc16(self)
+        mux1=Mux16(self,inc1,self.inc)
+        mux2=Mux16(mux1,self.a,self.load)
+        mux3=Mux16(mux2,Power([Power(False) for _ in range(16)]),self.reset)
+        for i in range(16):
+            self.mux3.out[i].out=mux3.out[i].out
+        self.register()
+        for i in range(16):
+            self.out[i].out=self.register.out[i].out

Source/Components/Sequential_Logic/RAM32K.py

@@ -0,0 +1,23 @@
+from Source.Logic_Gates.DMux8Way import DMux8Way
+from Source.Logic_Gates.Mux8Way16 import Mux8Way16
+from Source.Components.Sequential_Logic.RAM4K import RAM4K
+from Source.Pre_Built_Gates.Power import Power
+
+class RAM32K:
+    def __init__(self,a,load,address) -> None:
+        self.a=a
+        self.load=load
+        self.address=address
+        self.dmux=Power([Power(False) for _ in range(16)])
+        self.ram=Power([RAM4K(self.a,self.dmux.out[i],Power(self.address.out[3:15])) for i in range(8)])
+        self.out=[Power(False) for _ in range(16)]
+        self()
+    def __call__(self) -> None:
+        dmux=DMux8Way(self.load,Power(self.address.out[0:3]))
+        for i in range(8):
+            self.dmux.out[i].out=dmux.out[i].out
+        for i in range(8):
+            self.ram.out[i]()
+        mux=Mux8Way16(self.ram.out[0],self.ram.out[1],self.ram.out[2],self.ram.out[3],self.ram.out[4],self.ram.out[5],self.ram.out[6],self.ram.out[7],Power(self.address.out[0:3]))
+        for i in range(16):
+            self.out[i].out=mux.out[i].out

Source/Components/Sequential_Logic/RAM4K.py

@@ -0,0 +1,23 @@
+from Source.Logic_Gates.DMux8Way import DMux8Way
+from Source.Logic_Gates.Mux8Way16 import Mux8Way16
+from Source.Components.Sequential_Logic.RAM512 import RAM512
+from Source.Pre_Built_Gates.Power import Power
+
+class RAM4K:
+    def __init__(self,a,load,address):
+        self.a=a
+        self.load=load
+        self.address=address
+        self.dmux=Power([Power(False) for _ in range(16)])
+        self.ram=Power([RAM512(self.a,self.dmux.out[i],Power(self.address.out[3:12])) for i in range(8)])
+        self.out=[Power(False) for _ in range(16)]
+        self()
+    def __call__(self) -> None:
+        dmux=DMux8Way(self.load,Power(self.address.out[0:3]))
+        for i in range(8):
+            self.dmux.out[i].out=dmux.out[i].out
+        for i in range(8):
+            self.ram.out[i]()
+        mux=Mux8Way16(self.ram.out[0],self.ram.out[1],self.ram.out[2],self.ram.out[3],self.ram.out[4],self.ram.out[5],self.ram.out[6],self.ram.out[7],Power(self.address.out[0:3]))
+        for i in range(16):
+            self.out[i].out=mux.out[i].out

Source/Components/Sequential_Logic/RAM512.py

@@ -0,0 +1,23 @@
+from Source.Logic_Gates.DMux8Way import DMux8Way
+from Source.Logic_Gates.Mux8Way16 import Mux8Way16
+from Source.Components.Sequential_Logic.RAM64 import RAM64
+from Source.Pre_Built_Gates.Power import Power
+
+class RAM512:
+    def __init__(self,a,load,address):
+        self.a=a
+        self.load=load
+        self.address=address
+        self.dmux=Power([Power(False) for _ in range(16)])
+        self.ram=Power([RAM64(self.a,self.dmux.out[i],Power(self.address.out[3:9])) for i in range(8)])
+        self.out=[Power(False) for _ in range(16)]
+        self()
+    def __call__(self) -> None:
+        dmux=DMux8Way(self.load,Power(self.address.out[0:3]))
+        for i in range(8):
+            self.dmux.out[i].out=dmux.out[i].out
+        for i in range(8):
+            self.ram.out[i]()
+        mux=Mux8Way16(self.ram.out[0],self.ram.out[1],self.ram.out[2],self.ram.out[3],self.ram.out[4],self.ram.out[5],self.ram.out[6],self.ram.out[7],Power(self.address.out[0:3]))
+        for i in range(16):
+            self.out[i].out=mux.out[i].out

Source/Components/Sequential_Logic/RAM64.py

@@ -0,0 +1,23 @@
+from Source.Logic_Gates.DMux8Way import DMux8Way
+from Source.Logic_Gates.Mux8Way16 import Mux8Way16
+from Source.Components.Sequential_Logic.RAM8 import RAM8
+from Source.Pre_Built_Gates.Power import Power
+
+class RAM64:
+    def __init__(self,a,load,address):
+        self.a=a
+        self.load=load
+        self.address=address
+        self.dmux=Power([Power(False) for _ in range(16)])
+        self.ram=Power([RAM8(self.a,self.dmux.out[i],Power(self.address.out[3:6])) for i in range(8)])
+        self.out=[Power(False) for _ in range(16)]
+        self()
+    def __call__(self) -> None:
+        dmux=DMux8Way(self.load,Power(self.address.out[0:3]))
+        for i in range(8):
+            self.dmux.out[i].out=dmux.out[i].out
+        for i in range(8):
+            self.ram.out[i]()
+        mux=Mux8Way16(self.ram.out[0],self.ram.out[1],self.ram.out[2],self.ram.out[3],self.ram.out[4],self.ram.out[5],self.ram.out[6],self.ram.out[7],Power(self.address.out[0:3]))
+        for i in range(16):
+            self.out[i].out=mux.out[i].out

Source/Components/Sequential_Logic/RAM8.py

@@ -0,0 +1,23 @@
+from Source.Logic_Gates.DMux8Way import DMux8Way
+from Source.Logic_Gates.Mux8Way16 import Mux8Way16
+from Source.Components.Sequential_Logic.Register import Register
+from Source.Pre_Built_Gates.Power import Power
+
+class RAM8:
+    def __init__(self,a,load,address) -> None:
+        self.a=a
+        self.load=load
+        self.address=address
+        self.dmux=Power([Power(False) for _ in range(16)])
+        self.registers=Power([Register(self.a,self.dmux.out[i]) for i in range(8)])
+        self.out=[Power(False) for _ in range(16)]
+        self()
+    def __call__(self) -> None:
+        dmux=DMux8Way(self.load,self.address)
+        for i in range(8):
+            self.dmux.out[i].out=dmux.out[i].out
+        for i in range(8):
+            self.registers.out[i]()
+        mux=Mux8Way16(self.registers.out[0],self.registers.out[1],self.registers.out[2],self.registers.out[3],self.registers.out[4],self.registers.out[5],self.registers.out[6],self.registers.out[7],self.address)
+        for i in range(16):
+            self.out[i].out=mux.out[i].out

Source/Components/Sequential_Logic/Register.py

@@ -0,0 +1,14 @@
+from Source.Components.Sequential_Logic.Bit import Bit
+from Source.Pre_Built_Gates.Power import Power
+
+class Register:
+    def __init__(self,a,load) -> None:
+        self.a=a
+        self.load=load
+        self.bits=[Bit(self.a.out[i],self.load) for i in range(16)]
+        self.out=[Power(False) for _ in range(16)]
+        self()
+    def __call__(self) -> None:
+        for i in range(16):
+            self.bits[i]()
+            self.out[i].out=self.bits[i].out

Source/Computer.py

@@ -0,0 +1,22 @@
+from Source.Components.ROM32K import ROM32K
+from Source.Components.Memory import Memory
+from Source.Components.CPU import CPU
+from Source.Pre_Built_Gates.Power import Power
+
+class Computer:
+    def __init__(self,reset,file_path) -> None:
+        self.reset=reset
+        self.address=Power([Power(False) for _ in range(15)])
+        self.inM=Power([Power(False) for _ in range(16)])
+        self.ROM=ROM32K(self.address,file_path)
+        self.CPU=CPU(self.inM,self.ROM,self.reset)
+        self.Memory=Memory(self.CPU.out[0],self.CPU.out[1],self.CPU.out[2])
+        self()
+    def __call__(self) -> None:
+        self.ROM()
+        self.CPU()
+        self.Memory()
+        for i in range(15):
+            self.address.out[i].out=self.CPU.out[3].out[i].out
+        for i in range(16):
+            self.inM.out[i].out=self.Memory.out[i].out

Source/Logic_Gates/And16.py

@@ -0,0 +1,12 @@
+from Source.Pre_Built_Gates.And import And
+from Source.Pre_Built_Gates.Power import Power
+
+class And16:
+    def __init__(self,a,b) -> None:
+        self.a=a
+        self.b=b
+        self.out=[Power(False) for _ in range(16)]
+        self()
+    def __call__(self) -> None:
+        for i in range(16):
+            self.out[i].out=And(self.a.out[i],self.b.out[i]).out 

Source/Logic_Gates/DMux.py

@@ -0,0 +1,16 @@
+from Source.Pre_Built_Gates.And import And
+from Source.Pre_Built_Gates.Not import Not
+from Source.Pre_Built_Gates.Power import Power
+
+class DMux:
+    def __init__(self,a,sel) -> None:
+        self.a=a
+        self.sel=sel
+        self.out=[Power(False),Power(False)]
+        self()
+    def __call__(self) -> None:
+        negSel=Not(self.sel)
+        out1=And(self.a,negSel)
+        out2=And(self.a,self.sel)
+        self.out[0].out=out1.out
+        self.out[1].out=out2.out

Source/Logic_Gates/DMux8Way.py

@@ -0,0 +1,25 @@
+from Source.Logic_Gates.DMux import DMux
+from Source.Pre_Built_Gates.Power import Power
+
+class DMux8Way:
+    def __init__(self,a,sel) -> None:
+        self.a=a
+        self.sel=sel
+        self.out=[Power(False) for _ in range(8)]
+        self()
+    def __call__(self):
+        dmux1=DMux(self.a,self.sel.out[0])
+        dmux2=DMux(dmux1.out[0],self.sel.out[1])
+        dmux3=DMux(dmux1.out[1],self.sel.out[1])
+        dmux4=DMux(dmux2.out[0],self.sel.out[2])
+        dmux5=DMux(dmux2.out[1],self.sel.out[2])
+        dmux6=DMux(dmux3.out[0],self.sel.out[2])
+        dmux7=DMux(dmux3.out[1],self.sel.out[2])
+        self.out[0].out=dmux4.out[0].out
+        self.out[1].out=dmux4.out[1].out
+        self.out[2].out=dmux5.out[0].out
+        self.out[3].out=dmux5.out[1].out
+        self.out[4].out=dmux6.out[0].out
+        self.out[5].out=dmux6.out[1].out
+        self.out[6].out=dmux7.out[0].out
+        self.out[7].out=dmux7.out[1].out

Source/Logic_Gates/Mux.py

@@ -0,0 +1,17 @@
+from Source.Pre_Built_Gates.And import And
+from Source.Pre_Built_Gates.Not import Not
+from Source.Pre_Built_Gates.Or import Or
+
+class Mux:
+    def __init__(self,a,b,sel) -> None:
+        self.a=a
+        self.b=b
+        self.sel=sel
+        self.out=None
+        self()
+    def __call__(self) -> None:
+        negSel=Not(self.sel)
+        out1=And(self.a,negSel)
+        out2=And(self.b,self.sel)
+        out3=Or(out1,out2)
+        self.out=out3.out

Source/Logic_Gates/Mux16.py

@@ -0,0 +1,12 @@
+from Source.Logic_Gates.Mux import Mux
+from Source.Pre_Built_Gates.Power import Power
+class Mux16:
+    def __init__(self,a,b,sel) -> None:
+        self.a=a
+        self.b=b
+        self.sel=sel
+        self.out=[Power(False) for _ in range(16)]
+        self()
+    def __call__(self) -> None:
+        for i in range(16):
+            self.out[i].out=Mux(self.a.out[i],self.b.out[i],self.sel).out

Source/Logic_Gates/Mux8Way16.py

@@ -0,0 +1,26 @@
+from Source.Logic_Gates.Mux16 import Mux16
+from Source.Pre_Built_Gates.Power import Power
+
+class Mux8Way16:
+    def __init__(self,a,b,c,d,e,f,g,h,sel) -> None:
+        self.a=a
+        self.b=b
+        self.c=c
+        self.d=d
+        self.e=e
+        self.f=f
+        self.g=g
+        self.h=h
+        self.sel=sel
+        self.out=[Power(False) for _ in range(16)]
+        self()
+    def __call__(self):
+        mux1=Mux16(self.a,self.b,self.sel.out[2])
+        mux2=Mux16(self.c,self.d,self.sel.out[2])
+        mux3=Mux16(self.e,self.f,self.sel.out[2])
+        mux4=Mux16(self.g,self.h,self.sel.out[2])
+        mux5=Mux16(mux1,mux2,self.sel.out[1])
+        mux6=Mux16(mux3,mux4,self.sel.out[1])
+        mux7=Mux16(mux5,mux6,self.sel.out[0])
+        for i in range(16):
+            self.out[i].out=mux7.out[i].out

Source/Logic_Gates/Nand.py

@@ -0,0 +1,13 @@
+from Source.Pre_Built_Gates.Not import Not
+from Source.Pre_Built_Gates.And import And
+
+class Nand:
+    def __init__(self,a,b) -> None:
+        self.a=a
+        self.b=b
+        self.out=None
+        self()
+    def __call__(self) -> None:
+        out1=And(self.a,self.b)
+        out2=Not(out1)
+        self.out=out2.out

Source/Logic_Gates/Not16.py

@@ -0,0 +1,11 @@
+from Source.Pre_Built_Gates.Not import Not
+from Source.Pre_Built_Gates.Power import Power
+
+class Not16:
+    def __init__(self,a) -> None:
+        self.a=a
+        self.out=[Power(False) for _ in range(16)]
+        self()
+    def __call__(self) -> None:
+        for i in range(16):
+            self.out[i].out=Not(self.a.out[i]).out

Source/Logic_Gates/Or16.py

@@ -0,0 +1,12 @@
+from Source.Pre_Built_Gates.Or import Or
+from Source.Pre_Built_Gates.Power import Power
+
+class Or16:
+    def __init__(self,a,b) -> None:
+        self.a=a
+        self.b=b
+        self.out=[Power(False) for _ in range(16)]
+        self()
+    def __call__(self) -> None:
+        for i in range(16):
+            self.out[i].out=Or(self.a.out[i],self.b.out[i]).out

Source/Logic_Gates/Or8Way.py

@@ -0,0 +1,16 @@
+from Source.Pre_Built_Gates.Or import Or
+
+class Or8Way:
+    def __init__(self,a) -> None:
+        self.a=a
+        self.out=None
+        self()
+    def __call__(self) -> None:
+        or1=Or(self.a.out[0],self.a.out[1])
+        or2=Or(self.a.out[2],self.a.out[3])
+        or3=Or(self.a.out[4],self.a.out[5])
+        or4=Or(self.a.out[6],self.a.out[7])
+        or5=Or(or1,or2)
+        or6=Or(or3,or4)
+        or7=Or(or5,or6)
+        self.out=or7.out

Source/Logic_Gates/Xor.py

@@ -0,0 +1,15 @@
+from Source.Pre_Built_Gates.Or import Or
+from Source.Pre_Built_Gates.And import And
+from Source.Logic_Gates.Nand import Nand
+
+class Xor:
+    def __init__(self,a,b) -> None:
+        self.a=a
+        self.b=b
+        self.out=None
+        self()
+    def __call__(self) -> None:
+        out1=Or(self.a,self.b)
+        out2=Nand(self.a,self.b)
+        out3=And(out1,out2)
+        self.out=out3.out

Source/Pre_Built_Gates/And.py

@@ -0,0 +1,8 @@
+class And:
+    def __init__(self,a,b) -> None:
+        self.a = a
+        self.b = b
+        self.out=None
+        self()
+    def __call__(self) -> None:
+        self.out = self.a.out and self.b.out