Initial Commit

Source/Components/Sequential_Logic/Bit.py

@@ -0,0 +1,16 @@
+from Source.Pre_Built_Gates.FlipFlop import FlipFlop
+from Source.Logic_Gates.Mux import Mux
+
+class Bit:
+    def __init__(self,a,load) -> None:
+        self.a=a
+        self.load=load
+        self.out=None
+        self.mux=Mux(self,self.a,self.load)
+        self.flipflop=FlipFlop(self.mux)
+        self()
+    def __call__(self) -> None:
+        self.mux()
+        self.flipflop()
+        self.out=self.mux.out
+

Source/Components/Sequential_Logic/PC.py

@@ -0,0 +1,25 @@
+from Source.Logic_Gates.Mux16 import Mux16
+from Source.Components.Boolean_Arithmetic.Inc16 import Inc16
+from Source.Components.Sequential_Logic.Register import Register
+from Source.Pre_Built_Gates.Power import Power
+
+class PC:
+    def __init__(self,a,load,inc,reset) -> None:
+        self.a=a
+        self.load=load
+        self.inc=inc
+        self.reset=reset
+        self.out=[Power(False) for _ in range(16)]
+        self.mux3=Power([Power(False) for _ in range(16)])
+        self.register=Register(self.mux3,Power(True))
+        self()
+    def __call__(self) -> None:
+        inc1=Inc16(self)
+        mux1=Mux16(self,inc1,self.inc)
+        mux2=Mux16(mux1,self.a,self.load)
+        mux3=Mux16(mux2,Power([Power(False) for _ in range(16)]),self.reset)
+        for i in range(16):
+            self.mux3.out[i].out=mux3.out[i].out
+        self.register()
+        for i in range(16):
+            self.out[i].out=self.register.out[i].out

Source/Components/Sequential_Logic/RAM32K.py

@@ -0,0 +1,23 @@
+from Source.Logic_Gates.DMux8Way import DMux8Way
+from Source.Logic_Gates.Mux8Way16 import Mux8Way16
+from Source.Components.Sequential_Logic.RAM4K import RAM4K
+from Source.Pre_Built_Gates.Power import Power
+
+class RAM32K:
+    def __init__(self,a,load,address) -> None:
+        self.a=a
+        self.load=load
+        self.address=address
+        self.dmux=Power([Power(False) for _ in range(16)])
+        self.ram=Power([RAM4K(self.a,self.dmux.out[i],Power(self.address.out[3:15])) for i in range(8)])
+        self.out=[Power(False) for _ in range(16)]
+        self()
+    def __call__(self) -> None:
+        dmux=DMux8Way(self.load,Power(self.address.out[0:3]))
+        for i in range(8):
+            self.dmux.out[i].out=dmux.out[i].out
+        for i in range(8):
+            self.ram.out[i]()
+        mux=Mux8Way16(self.ram.out[0],self.ram.out[1],self.ram.out[2],self.ram.out[3],self.ram.out[4],self.ram.out[5],self.ram.out[6],self.ram.out[7],Power(self.address.out[0:3]))
+        for i in range(16):
+            self.out[i].out=mux.out[i].out

Source/Components/Sequential_Logic/RAM4K.py

@@ -0,0 +1,23 @@
+from Source.Logic_Gates.DMux8Way import DMux8Way
+from Source.Logic_Gates.Mux8Way16 import Mux8Way16
+from Source.Components.Sequential_Logic.RAM512 import RAM512
+from Source.Pre_Built_Gates.Power import Power
+
+class RAM4K:
+    def __init__(self,a,load,address):
+        self.a=a
+        self.load=load
+        self.address=address
+        self.dmux=Power([Power(False) for _ in range(16)])
+        self.ram=Power([RAM512(self.a,self.dmux.out[i],Power(self.address.out[3:12])) for i in range(8)])
+        self.out=[Power(False) for _ in range(16)]
+        self()
+    def __call__(self) -> None:
+        dmux=DMux8Way(self.load,Power(self.address.out[0:3]))
+        for i in range(8):
+            self.dmux.out[i].out=dmux.out[i].out
+        for i in range(8):
+            self.ram.out[i]()
+        mux=Mux8Way16(self.ram.out[0],self.ram.out[1],self.ram.out[2],self.ram.out[3],self.ram.out[4],self.ram.out[5],self.ram.out[6],self.ram.out[7],Power(self.address.out[0:3]))
+        for i in range(16):
+            self.out[i].out=mux.out[i].out

Source/Components/Sequential_Logic/RAM512.py

@@ -0,0 +1,23 @@
+from Source.Logic_Gates.DMux8Way import DMux8Way
+from Source.Logic_Gates.Mux8Way16 import Mux8Way16
+from Source.Components.Sequential_Logic.RAM64 import RAM64
+from Source.Pre_Built_Gates.Power import Power
+
+class RAM512:
+    def __init__(self,a,load,address):
+        self.a=a
+        self.load=load
+        self.address=address
+        self.dmux=Power([Power(False) for _ in range(16)])
+        self.ram=Power([RAM64(self.a,self.dmux.out[i],Power(self.address.out[3:9])) for i in range(8)])
+        self.out=[Power(False) for _ in range(16)]
+        self()
+    def __call__(self) -> None:
+        dmux=DMux8Way(self.load,Power(self.address.out[0:3]))
+        for i in range(8):
+            self.dmux.out[i].out=dmux.out[i].out
+        for i in range(8):
+            self.ram.out[i]()
+        mux=Mux8Way16(self.ram.out[0],self.ram.out[1],self.ram.out[2],self.ram.out[3],self.ram.out[4],self.ram.out[5],self.ram.out[6],self.ram.out[7],Power(self.address.out[0:3]))
+        for i in range(16):
+            self.out[i].out=mux.out[i].out

Source/Components/Sequential_Logic/RAM64.py

@@ -0,0 +1,23 @@
+from Source.Logic_Gates.DMux8Way import DMux8Way
+from Source.Logic_Gates.Mux8Way16 import Mux8Way16
+from Source.Components.Sequential_Logic.RAM8 import RAM8
+from Source.Pre_Built_Gates.Power import Power
+
+class RAM64:
+    def __init__(self,a,load,address):
+        self.a=a
+        self.load=load
+        self.address=address
+        self.dmux=Power([Power(False) for _ in range(16)])
+        self.ram=Power([RAM8(self.a,self.dmux.out[i],Power(self.address.out[3:6])) for i in range(8)])
+        self.out=[Power(False) for _ in range(16)]
+        self()
+    def __call__(self) -> None:
+        dmux=DMux8Way(self.load,Power(self.address.out[0:3]))
+        for i in range(8):
+            self.dmux.out[i].out=dmux.out[i].out
+        for i in range(8):
+            self.ram.out[i]()
+        mux=Mux8Way16(self.ram.out[0],self.ram.out[1],self.ram.out[2],self.ram.out[3],self.ram.out[4],self.ram.out[5],self.ram.out[6],self.ram.out[7],Power(self.address.out[0:3]))
+        for i in range(16):
+            self.out[i].out=mux.out[i].out

Source/Components/Sequential_Logic/RAM8.py

@@ -0,0 +1,23 @@
+from Source.Logic_Gates.DMux8Way import DMux8Way
+from Source.Logic_Gates.Mux8Way16 import Mux8Way16
+from Source.Components.Sequential_Logic.Register import Register
+from Source.Pre_Built_Gates.Power import Power
+
+class RAM8:
+    def __init__(self,a,load,address) -> None:
+        self.a=a
+        self.load=load
+        self.address=address
+        self.dmux=Power([Power(False) for _ in range(16)])
+        self.registers=Power([Register(self.a,self.dmux.out[i]) for i in range(8)])
+        self.out=[Power(False) for _ in range(16)]
+        self()
+    def __call__(self) -> None:
+        dmux=DMux8Way(self.load,self.address)
+        for i in range(8):
+            self.dmux.out[i].out=dmux.out[i].out
+        for i in range(8):
+            self.registers.out[i]()
+        mux=Mux8Way16(self.registers.out[0],self.registers.out[1],self.registers.out[2],self.registers.out[3],self.registers.out[4],self.registers.out[5],self.registers.out[6],self.registers.out[7],self.address)
+        for i in range(16):
+            self.out[i].out=mux.out[i].out

Source/Components/Sequential_Logic/Register.py

@@ -0,0 +1,14 @@
+from Source.Components.Sequential_Logic.Bit import Bit
+from Source.Pre_Built_Gates.Power import Power
+
+class Register:
+    def __init__(self,a,load) -> None:
+        self.a=a
+        self.load=load
+        self.bits=[Bit(self.a.out[i],self.load) for i in range(16)]
+        self.out=[Power(False) for _ in range(16)]
+        self()
+    def __call__(self) -> None:
+        for i in range(16):
+            self.bits[i]()
+            self.out[i].out=self.bits[i].out