60 lines
2.8 KiB
Python
60 lines
2.8 KiB
Python
from Source.Pre_Built_Gates.Not import Not
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from Source.Pre_Built_Gates.And import And
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from Source.Pre_Built_Gates.Or import Or
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from Source.Pre_Built_Gates.Power import Power
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from Source.Logic_Gates.Mux16 import Mux16
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from Source.Components.Boolean_Arithmetic.ALU import ALU
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from Source.Components.Sequential_Logic.Register import Register
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from Source.Components.Sequential_Logic.PC import PC
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class CPU:
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def __init__(self,inM,instruction,reset) -> None:
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self.inM=inM
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self.instruction=instruction
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self.reset=reset
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self.out=[Power([Power(False) for _ in range(16)]),Power(False),Power([Power(False) for _ in range(15)]),Power([Power(False) for _ in range(15)])]
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self.mux=Power([Power(False) for _ in range(16)])
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self.ALUout=Power([Power(False) for _ in range(16)])
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self.a_load=Power(False)
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self.d_load=Power(False)
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self.PC_load=Power(False)
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self.A_register=Register(self.mux,self.a_load)
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self.D_register=Register(self.ALUout,self.d_load)
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self.PC=PC(self.A_register,self.PC_load,Power(True),self.reset)
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self()
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def __call__(self) -> None:
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not1=Not(self.instruction.out[0])
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mux1=Mux16(self.ALUout,self.instruction,not1)
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for i in range(16):
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self.mux.out[i].out=mux1.out[i].out
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a_load=Or(not1,self.instruction.out[10])
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self.a_load.out=a_load.out
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self.A_register()
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and1=And(self.instruction.out[0],self.instruction.out[3])
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mux2=Mux16(self.A_register,self.inM,and1)
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d_load=And(self.instruction.out[0],self.instruction.out[11])
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self.d_load.out=d_load.out
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alu=ALU(self.D_register,mux2,self.instruction.out[4],self.instruction.out[5],self.instruction.out[6],self.instruction.out[7],self.instruction.out[8],self.instruction.out[9])
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for i in range(16):
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self.ALUout.out[i].out=alu.out[0].out[i].out
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self.D_register()
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and3=And(self.instruction.out[0],self.instruction.out[12])
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poz=Not(alu.out[2])
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non_zero=Not(alu.out[1])
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jgt=And(self.instruction.out[0],self.instruction.out[15])
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poz_non_zero=And(poz,non_zero)
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jmp1=And(jgt,poz_non_zero)
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jeq=And(self.instruction.out[0],self.instruction.out[14])
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jmp2=And(jeq,alu.out[1])
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jlt=And(self.instruction.out[0],self.instruction.out[13])
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jmp3=And(jlt,alu.out[2])
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jmp4=Or(jmp1,jmp2)
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jmp5=Or(jmp4,jmp3)
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self.PC_load.out=jmp5.out
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self.PC()
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for i in range(16):
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self.out[0].out[i].out=alu.out[0].out[i].out
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self.out[1].out=and3.out
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for i in range(15):
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self.out[2].out[i].out=self.A_register.out[i+1].out
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self.out[3].out[i].out=self.PC.out[i+1].out |